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Freescale Semiconductor, Inc.
MC68HC908QF4
Freescale Semiconductor, Inc...
Data Sheet
M68HC08
Microcontrollers
MC68HC908QF4 Rev. 1.0 6/2004
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Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc.
MC68HC908QF4
Data Sheet
Freescale Semiconductor, Inc...
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://motorola.com/semiconductors/ The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location.
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
Data Sheet 3
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Revision History
Revision History
Date October, 2003 Revision Level N/A Initial release Removed references to MC68HC908QF3, MC68HC908QF2, and MC68HC908QF1 1.0 17.4 Thermal Characteristics -- Updated 32-pin TQFP value 18.2 MC Order Numbers -- Updated table entries for MC order numbers Description Page Number(s) N/A Throughout 176 193
June, 2004
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Data Sheet 4 Revision History
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Freescale Semiconductor, Inc.
Data Sheet -- MC68HC908QF4
List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Section 3. Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . 37
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Section 4. Auto Wakeup Module (AWU) . . . . . . . . . . . . . . . . . . . . . . . . 45 Section 5. Configuration Register (CONFIG) . . . . . . . . . . . . . . . . . . . . 51 Section 6. Computer Operating Properly (COP) . . . . . . . . . . . . . . . . . 55 Section 7. Central Processor Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . 59 Section 8. External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Section 9. Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . 79 Section 10. Low-Voltage Inhibit (LVI) . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Section 11. Oscillator Module (OSC). . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Section 12. PLL Tuned UHF Transmitter Module. . . . . . . . . . . . . . . . 101 Section 13. Input/Output (I/O) Ports . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Section 14. System Integration Module (SIM) . . . . . . . . . . . . . . . . . . 119 Section 15. Timer Interface Module (TIM) . . . . . . . . . . . . . . . . . . . . . . 137 Section 16. Development Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Section 17. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 175 Section 18. Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
MC68HC908QF4 -- Rev. 1.0 MOTOROLA List of Sections
Data Sheet 5
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List of Sections
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Data Sheet 6 List of Sections
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Freescale Semiconductor, Inc.
Data Sheet -- MC68HC908QF4
Table of Contents
Section 1. General Description
1.1 1.2 1.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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1.4 1.5
Section 2. Memory
2.1 2.2 2.3 2.4 2.5 2.6 2.6.1 2.6.2 2.6.3 2.6.4 2.6.5 2.6.6 2.6.7 2.6.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 FLASH Memory (FLASH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 30 31 32 32 33 35 36 36
Section 3. Analog-to-Digital Converter (ADC)
3.1 3.2 3.3 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Port I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conversion Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 40 40 40 40 40
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Table of Contents
Data Sheet 7
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Table of Contents
3.5 3.5.1 3.5.2 3.6 3.7 3.7.1 3.7.2 3.7.3
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Input/Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Input Clock Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 42 43 44
Section 4. Auto Wakeup Module (AWU)
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4.1 4.2 4.3 4.4 4.5 4.6 4.6.1 4.6.2 4.6.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A I/O Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . Keyboard Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . 47 48 48 49
Section 5. Configuration Register (CONFIG)
5.1 5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Section 6. Computer Operating Properly (COP)
6.1 6.2 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.3.7 6.4 6.5 6.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUSCLKX4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STOP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COPD (COP Disable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 56 56 56 56 56 57 57
COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Data Sheet 8 Table of Contents
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Table of Contents
6.7 6.7.1 6.7.2 6.8
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Section 7. Central Processor Unit (CPU)
7.1 7.2 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.4 7.5 7.5.1 7.5.2 7.6 7.7 7.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Index Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Condition Code Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 60 61 61 62 62
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Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Section 8. External Interrupt (IRQ)
8.1 8.2 8.3 8.4 8.5 8.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Section 9. Keyboard Interrupt Module (KBI)
9.1 9.2 9.3 9.3.1 9.3.2 9.4 9.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Keyboard Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Keyboard Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Table of Contents
Data Sheet 9
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Table of Contents
9.6 9.7 9.7.1 9.7.2
Keyboard Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . 83 Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Keyboard Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . 84 Keyboard Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . 85
Section 10. Low-Voltage Inhibit (LVI)
10.1 10.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 87 88 88 88 89
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10.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.1 Polled LVI Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.2 Forced Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.3 Voltage Hysteresis Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.4 LVI Trip Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4 10.5
LVI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
10.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 10.6.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 10.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Section 11. Oscillator Module (OSC)
11.1 11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 91 91 93 93 94 94 95 95 95 96 96 96 96 97 97 97
11.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.1 Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.1.1 Internal Oscillator Trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.1.2 Internal to External Clock Switching . . . . . . . . . . . . . . . . . . . . . . . 11.3.2 External Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.3 XTAL Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.4 RC Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4 Oscillator Module Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4.1 Crystal Amplifier Input Pin (OSC1) . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4.2 Crystal Amplifier Output Pin (OSC2/PTA4/BUSCLKX4). . . . . . . . . . 11.4.3 Oscillator Enable Signal (SIMOSCEN) . . . . . . . . . . . . . . . . . . . . . . . 11.4.4 XTAL Oscillator Clock (XTALCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4.5 RC Oscillator Clock (RCCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4.6 Internal Oscillator Clock (INTCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4.7 Oscillator Out 2 (BUSCLKX4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4.8 Oscillator Out (BUSCLKX2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.5 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 11.5.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 11.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Data Sheet 10 Table of Contents
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Table of Contents
11.6 11.7
Oscillator During Break Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 CONFIG2 Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
11.8 Input/Output (I/O) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 11.8.1 Oscillator Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 11.8.2 Oscillator Trim Register (OSCTRIM) . . . . . . . . . . . . . . . . . . . . . . . . 99
Section 12. PLL Tuned UHF Transmitter Module
12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Transmitter Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Phase-Lock Loop (PLL) and Local Oscillator . . . . . . . . . . . . . . . . . . . . 103 RF Output Stage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Microcontroller Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 State Machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Data Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
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12.10 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 12.10.1 Application Schematics in OOK and FSK Modulation . . . . . . . . . . 107 12.10.2 Complete Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Section 13. Input/Output (I/O) Ports
13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 112 112 113 114 115 115 115 116 13.2 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.1 Port A Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.2 Data Direction Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.3 Port A Input Pullup Enable Register . . . . . . . . . . . . . . . . . . . . . . . . 13.3 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.1 Port B Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.2 Data Direction Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.3 Port B Input Pullup Enable Register . . . . . . . . . . . . . . . . . . . . . . . .
Section 14. System Integration Module (SIM)
14.1 14.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 RST and IRQ Pins Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 121 122 122 122
14.3 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . . . . . . . 14.3.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.2 Clock Start-Up from POR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . . . . . .
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14.4 Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . . . . . . 14.4.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4.2.2 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . . . 14.4.2.3 Illegal Opcode Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . . . . . . . 14.5 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . . . . . . 14.5.2 SIM Counter During Stop Mode Recovery . . . . . . . . . . . . . . . . . . . 14.5.3 SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6 Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6.1 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6.1.2 SWI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6.2 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6.2.1 Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6.2.2 Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6.2.3 Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6.4 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.6.5 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . . . . . .
122 123 123 124 124 125 125 125 126 126 126 126 126 126 128 129 130 130 131 131 131 131 132
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14.7 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 14.7.1 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 14.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 14.8 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 14.8.1 SIM Reset Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 14.8.2 Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Section 15. Timer Interface Module (TIM)
15.1 15.2 15.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 139 141 141 141 141 142 142 143 144 144
15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.4.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.4.3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.4.3.1 Unbuffered Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.4.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.4.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.4.4.1 Unbuffered PWM Signal Generation. . . . . . . . . . . . . . . . . . . . . . 15.4.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . 15.4.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Sheet 12 Table of Contents
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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15.5 15.6 15.7
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
15.8 Input/Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 15.8.1 TIM Clock Pin (PTA2/TCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 15.8.2 TIM Channel I/O Pins (PTA0/TCH0 and PTA1/TCH1) . . . . . . . . . . 146 15.9 Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.9.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . 15.9.2 TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.9.3 TIM Counter Modulo Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.9.4 TIM Channel Status and Control Registers . . . . . . . . . . . . . . . . . . 15.9.5 TIM Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 147 149 149 150 153
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Section 16. Development Support
16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 155 155 158 158 158 159 159 160 160 161 161 162 162 162 166 168 168 169 169 169 170 173 16.2 Break Module (BRK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2.1.1 Flag Protection During Break Interrupts . . . . . . . . . . . . . . . . . . . 16.2.1.2 TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2.1.3 COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2.2 Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2.2.1 Break Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . 16.2.2.2 Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2.2.3 Break Auxiliary Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2.2.4 Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2.2.5 Break Flag Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2.3 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3 Monitor Module (MON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3.1.1 Normal Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3.1.2 Forced Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3.1.3 Monitor Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3.1.4 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3.1.5 Break Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3.1.6 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3.1.7 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3.2 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 17. Electrical Specifications
17.1 17.2 17.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Table of Contents
Data Sheet 13
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17.4 17.5 17.6 17.7 17.8 17.9
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Typical 3.0-V Output Drive Characteristics. . . . . . . . . . . . . . . . . . . . . . 179 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
17.10 Analog-to-Digital (ADC) Converter Characteristics. . . . . . . . . . . . . . . . 183 17.10.1 ADC Electrical Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . 183 17.10.2 ADC Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 183
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17.11 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 184 17.12 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 17.13 UHF Transmitter Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 17.13.1 UHF Module Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 186 17.13.2 UHF Module Output Power Measurement . . . . . . . . . . . . . . . . . . . 190
Section 18. Ordering Information and Mechanical Specifications
18.1 18.2 18.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 32-Pin Plastic Low-Profile Quad Flat Pack (Case No. 873A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Data Sheet 14 Table of Contents
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Data Sheet -- MC68HC908QF4
Section 1. General Description
1.1 Introduction
The MC68HC908QF4 MCU is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). Optimized for low-power operation and available in a small 32-pin low-profile quad flat pack (LQFP), this MCU is well suited for remote keyless entry (RKE) transmitter designs, tire pressure monitoring (TPM), or other remote sensing and wireless RF data transmission applications. All MCUs in the M68HC908 Family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types.
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1.2 Features
Features of the MC68HC908QF4 MCU include: * * * * * High-performance M68HC08 architecture Fully upward-compatible object code with M6805, M146805, and M68HC05 Families Operating voltage range of 2.2 to 3.6 V Maximum internal bus frequency of 2 MHz Trimmable internal oscillator - 4-MHz operating frequency for a 1-MHz bus frequency - 8-bit trim capability allows 0.4% accuracy(1) - 25 percent accuracy untrimmed Auto wakeup from STOP capability 4096 bytes of on-chip FLASH memory FLASH program memory security(2) 128 bytes of on-chip RAM 16-bit, 2-channel timer interface module (TIM) 4 channel, 8-bit analog-to-digital converter (ADC)
* * * * * *
1. The oscillator frequency is guaranteed to 5% over temperature and voltage range after trimming. 2. No security feature is absolutely secure. However, Motorola's strategy is to make reading or copying the FLASH difficult for unauthorized users.
MC68HC908QF4 -- Rev. 1.0 MOTOROLA General Description
Data Sheet 15
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General Description
*
13 general-purpose input/output (I/O) ports: - Six shared with keyboard wakeup function - Three shared with the timer module, IRQ - Port A pins have 3-mA sink capabilities Low-voltage inhibit (LVI) module with selectable trip points: - 2.12 V detection forces MCU into reset - 2.32 V detection sets indicator flag 6-bit keyboard interrupt with wakeup feature (KBI) External asynchronous interrupt pin with internal pullup (IRQ) Ultra high frequency (UHF) RF transmitter: - Ultra low sleep mode current - ASK and FSK modulation selectable System protection features: - Computer operating properly (COP) reset - Low-voltage detection with reset - Illegal opcode detection with reset - Illegal address detection with reset 32-pin plastic LQFP package Power saving stop and wait modes Master reset pin (RST) shared with general-purpose I/O pin
*
* * *
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*
* * *
Features of the CPU08 include: * * * * * * * * * * Enhanced HC05 programming model Extensive loop control functions 16 addressing modes (eight more than the HC05) 16-bit index register and stack pointer Memory-to-memory data transfers Fast 8 x 8 multiply instruction Fast 16/8 divide instruction Binary-coded decimal (BCD) instructions Optimization for controller applications Third party C language support
1.3 MCU Block Diagram
Figure 1-1 shows the structure of the MC68HC908QF4 MCU.
Data Sheet 16 General Description
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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General Description Pin Assignments
PTA0/AD0/TCH0/KBI0 PTA1/AD1/TCH1/KBI1 DDRA PTA PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 M68HC08 CPU PTB0 PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 CLOCK GENERATOR (OSCILLATOR)
SYSTEM INTEGRATION MODULE SINGLE INTERRUPT MODULE BREAK MODULE POWER-ON RESET MODULE KEYBOARD INTERRUPT MODULE 16-BIT TIMER MODULE COP MODULE VCC MODE PLLEN DATA BS OP1 GND REXT XTAL1 XTAL0 UPCLK PFD
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8-BIT ADC
DDRB
PTB
MC68HC908QF4 4096 BYTES USER FLASH
128 BYTES RAM
MONITOR ROM
UHF TRANSMITTER
VDD POWER SUPPLY VSS
RST, IRQ: Pins have internal (about 30K Ohms) pull up PTA[0:5]: High current sink and source capability PTA[0:5]: Pins have programmable keyboard interrupt and pull up
Figure 1-1. Block Diagram
1.4 Pin Assignments
The MC68HC908QF4 is available in a 32-pin plastic low-profile quad flat pack (LQFP). Figure 1-2 shows the pin assignment for this package.
MC68HC908QF4 -- Rev. 1.0 MOTOROLA General Description
Data Sheet 17
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General Description
1.5 Pin Functions
Table 1-1 provides a description of the pin functions other than those dedicated to the UHF module which are shown in Table 1-2.
PTA4/OSC2/KBI4
PTA5/OSC1/KBI5
PTB4
PTB5
PTB6 26
32
31
30
29
28
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PTA3/RST/KBI3 PTA2/IRQ/KBI2 PTB3 PTB2 PTA1/TCH1/KBI1 GND XTAL1 XTAL0
27
25
PTB7
NC
NC
1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 9
24 23 22 21 20 19 18 17
VDD VSS PTB0 PTB1 PTA0/TCH0/KBI0 DATA CLK DATA BAND
Figure 1-2. MC68HC908QF4 Pin Assignments
Table 1-1. Pin Functions
Pin Name VDD VSS Power supply Power supply ground PTA0 -- General purpose I/O port PTA0 TCH0 -- Timer Channel 0 I/O KBI0 -- Keyboard interrupt input 0 PTA1 -- General purpose I/O port PTA1 TCH1 -- Timer Channel 1 I/O KBI1 -- Keyboard interrupt input 1 Description Input/Output Power Power Input/Output Input/Output Input Input/Output Input/Output Input
Data Sheet 18 General Description
ENABLE
RFOUT
GNDRF
MODE
VCC
CFSK
REXT
VCC
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General Description Pin Functions
Table 1-1. Pin Functions (Continued)
Pin Name Description PTA2 -- General purpose input-only port PTA2 IRQ -- External interrupt with programmable pullup and Schmitt trigger input KBI2 -- Keyboard interrupt input 2 PTA3 -- General purpose I/O port PTA3 RST -- Reset input, active low with internal pullup and Schmitt trigger KBI3 -- Keyboard interrupt input 3 PTA4 -- General purpose I/O port PTA4 OSC2 --XTAL oscillator output (XTAL option only) RC or internal oscillator output (OSC2EN = 1 in PTAPUE register) KBI4 -- Keyboard interrupt input 4 PTA5 -- General purpose I/O port PTA5 OSC1 --XTAL, RC, or external oscillator input KBI5 -- Keyboard interrupt input 5 PTB[0:7] 8 general-purpose I/O ports Input/Output Input Input Input Input/Output Input Input Input/Output Output Output Input Input/Output Input Input Input/Output
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Table 1-2. UHF Transmitter Pins
Pin 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Function GND XTAL1 XTAL0 REXT CFSK VCC RFOUT GNDRF VCC ENABLE MODE BAND DATA DATACLK Ground Reference oscillator input Reference oscillator output Output amplifier current setting resistor FSK switch output Power supply Power amplifier output Power amplifier ground Power supply Enable input Modulation type selection input Frequency band selection Data input Clock output to the microcontroller Description
MC68HC908QF4 -- Rev. 1.0 MOTOROLA General Description
Data Sheet 19
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General Description
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Data Sheet 20 General Description
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Data Sheet -- MC68HC908QF4
Section 2. Memory
2.1 Introduction
The central processor unit (CPU08) can address 64 Kbytes of memory space. The memory map, shown in Figure 2-1, includes: * 4096 bytes of user FLASH 128 bytes of random access memory (RAM) 48 bytes of user-defined vectors, located in FLASH 416 bytes of monitor read-only memory (ROM) 1536 bytes of FLASH program and erase routines, located in ROM
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* * * *
2.2 Unimplemented Memory Locations
Accessing an unimplemented location can have unpredictable effects on MCU operation. In Figure 2-1 and in register figures in this document, unimplemented locations are shaded.
2.3 Reserved Memory Locations
Accessing a reserved location can have unpredictable effects on MCU operation. In Figure 2-1 and in register figures in this document, reserved locations are marked with the word Reserved or with the letter R.
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Memory
Data Sheet 21
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Memory
$0000 $003F $0040 $007F $0080 $00FF $0100 $27FF $2800 $2DFF $2E00 $EDFF $EE00 $FDFF $FE00 $FE0F $FE10 $FFAF $FFB0 $FFBD $FFBE $FFBF $FFC0 $FFC1 $FFC2 $FFCF $FFD0 $FFFF
I/O REGISTERS 64 BYTES RESERVED 64 BYTES RAM 128 BYTES UNIMPLEMENTED 9984 BYTES AUXILIARY ROM 1536 BYTES UNIMPLEMENTED 49152 BYTES FLASH MEMORY 4096 BYTES
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SYSTEM REGISTERS
MONITOR ROM 416 BYTES
FLASH 14 BYTES FLASH BLOCK PROTECT REGISTER (FLBPR) RESERVED FLASH INTERNAL OSCILLATOR TRIM VALUE RESERVED FLASH FLASH 14 BYTES USER VECTORS 48 BYTES
Figure 2-1. Memory Map
Data Sheet 22 Memory
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Memory Input/Output (I/O) Section
2.4 Input/Output (I/O) Section
Addresses $0000-$003F, shown in Figure 2-2, contain most of the control, status, and data registers. Additional I/O registers have these addresses: * * * * * * * * * * * * * * * * * $FE00 -- Break status register, BSR $FE01 -- Reset status register, SRSR $FE02 -- Break auxiliary register, BRKAR $FE03 -- Break flag control register, BFCR $FE04 -- Interrupt status register 1, INT1 $FE05 -- Interrupt status register 2, INT2 $FE06 -- Interrupt status register 3, INT3 $FE07 -- Reserved $FE08 -- FLASH control register, FLCR $FE09 -- Break address register high, BRKH $FE0A -- Break address register low, BRKL $FE0B -- Break status and control register, BRKSCR $FE0C -- LVI status register, LVISR $FE0D -- Reserved $FFBE -- FLASH block protect register, FLBPR $FFC0 -- Internal OSC trim value -- Optional $FFFF -- COP control register, COPCTL
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MC68HC908QF4 -- Rev. 1.0 MOTOROLA
Data Sheet Memory 23
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Memory
Addr. $0000
Register Name Port A Data Register Read: (PTA) Write: See page 112. Reset: Port B Data Register Read: (PTB) Write: See page 115. Reset: Unimplemented
Bit 7 R
6 AWUL
5 PTA5
4 PTA4
3 PTA3
2 PTA2
1 PTA1
Bit 0 PTA0
UNAFFECTED BY RESET PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0
$0001 $0002 $0003
Unaffected by reset
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$0004
Data Direction Register A Read: (DDRA) Write: See page 113. Reset: Data Direction Register B Read: (DDRB) Write: See page 115. Reset: Unimplemented
R 0 DDRB7 0
R 0 DDRB6 0
DDRA5 0 DDRB5 0
DDRA4 0 DDRB4 0
DDRA3 0 DDRB3 0
0 0 DDRB2 0
DDRA1 0 DDRB1 0
DDRA0 0 DDRB0 0
$0005 $0006 $000A
$000B
Port A Input Pullup Enable Read: OSC2EN Register (PTAPUE) Write: See page 114. Reset: 0 Port B Input Pullup Enable Read: PTBPUE7 Register (PTBPUE) Write: See page 116. Reset: 0 Unimplemented
0 0 PTBPUE6 0
PTAPUE5 0 PTBPUE5 0
PTAPUE4 0 PTBPUE4 0
PTAPUE3 0 PTBPUE3 0
PTAPUE2 0 PTBPUE2 0
PTAPUE1 0 PTBPUE1 0
PTAPUE0 0 PTBPUE0 0
$000C $000D $0019
$001A
Keyboard Status and Read: Control Register (KBSCR) Write: See page 84. Reset: Keyboard Interrupt Read: Enable Register (KBIER) Write: See page 85. Reset: Unimplemented
0 0 0 0
0 0 AWUIE 0
0 0 KBIE5 0
0 0 KBIE4 0
KEYF 0 KBIE3 0
0 ACKK 0 KBIE2 0
IMASKK 0 KBIE1 0
MODEK 0 KBIE0 0
$001B $001C
= Unimplemented
R
= Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 5)
Data Sheet 24 Memory
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Memory Input/Output (I/O) Section
Addr. $001D
Register Name IRQ Status and Control Read: Register (INTSCR) Write: See page 77. Reset: Configuration Register 2 Read: (CONFIG2)(1) Write: See page 51. Reset:
Bit 7 0 0 IRQPUD 0
6 0 0 IRQEN 0
5 0 0 R 0
4 0 0
3 IRQF1 0
2 0 ACK1 0
1 IMASK1 0 R 0
Bit 0 MODE1 0 RSTEN 0(2)
$001E
OSCOPT1 OSCOPT0 0 0
R
0
1. One-time writable register after each reset. 2. RSTEN reset to 0 by a power-on reset (POR) only. Configuration Register 1 Read: (CONFIG1)(1) Write: See page 52. Reset:
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$001F
COPRS 0
LVISTOP 0
LVIRSTD 0
LVIPWRD 0
LVDLVR 0(2)
SSREC 0
STOP 0
COPD 0
1. One-time writable register after each reset. Exceptions are LVDLVR and LVIRSTD bits. 2. LVDLVR reset to 0 by a power-on reset (POR) only. TIM Status and Control Read: Register (TSC) Write: See page 147. Reset: TIM Counter Register High Read: (TCNTH) Write: See page 149. Reset: TIM Counter Register Low Read: (TCNTL) Write: See page 149. Reset: TIM Counter Modulo Read: Register High (TMODH) Write: See page 149. Reset: TIM Counter Modulo Read: Register Low (TMODL) Write: See page 149. Reset: TIM Channel 0 Status and Read: Control Register (TSC0) Write: See page 150. Reset: TIM Channel 0 Read: Register High (TCH0H) Write: See page 153. Reset: TOF 0 0 Bit 15 0 Bit 7 0 Bit 15 1 Bit 7 1 CH0F 0 0 Bit 15 0 TRST 0 Bit 12 0 Bit 4 0 Bit 12 1 Bit 4 1 MS0A 0 Bit 12 0 Bit 11 0 Bit 3 0 Bit 11 1 Bit 3 1 ELS0B 0 Bit 11 0
$0020
TOIE 0 Bit 14 0 Bit 6 0 Bit 14 1 Bit 6 1 CH0IE 0 Bit 14
TSTOP 1 Bit 13 0 Bit 5 0 Bit 13 1 Bit 5 1 MS0B 0 Bit 13
PS2 0 Bit 10 0 Bit 2 0 Bit 10 1 Bit 2 1 ELS0A 0 Bit 10
PS1 0 Bit 9 0 Bit 1 0 Bit 9 1 Bit 1 1 TOV0 0 Bit 9
PS0 0 Bit 8 0 Bit 0 0 Bit 8 1 Bit 0 1 CH0MAX 0 Bit 8
$0021
$0022
$0023
$0024
$0025
$0026
Indeterminate after reset = Unimplemented R = Reserved U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 5)
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Memory
Data Sheet 25
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Memory
Addr. $0027
Register Name TIM Channel 0 Read: Register Low (TCH0L) Write: See page 153. Reset: TIM Channel 1 Status and Read: Control Register (TSC1) Write: See page 150. Reset: TIM Channel 1 Read: Register High (TCH1H) Write: See page 153. Reset: TIM Channel 1 Read: Register Low (TCH1L) Write: See page 153. Reset: Unimplemented
Bit 7 Bit 7
6 Bit 6
5 Bit 5
4 Bit 4
3 Bit 3
2 Bit 2
1 Bit 1
Bit 0 Bit 0
Indeterminate after reset CH1F 0 0 Bit 15 CH1IE 0 Bit 14 0 0 Bit 13 MS1A 0 Bit 12 ELS1B 0 Bit 11 ELS1A 0 Bit 10 TOV1 0 Bit 9 CH1MAX 0 Bit 8
$0028
$0029
Indeterminate after reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
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$002A $002B $0035
Indeterminate after reset
$0036 $0037
Oscillator Status Register Read: (OSCSTAT) Write: See page 98. Reset: Unimplemented Read: Oscillator Trim Register Read: (OSCTRIM) Write: See page 99. Reset: Unimplemented
R 0
R 0
R 0
R 0
R 0
R 0
ECGON 0
ECGST 0
TRIM7 1
TRIM6 0
TRIM5 0
TRIM4 0
TRIM3 0
TRIM2 0
TRIM1 0
TRIM0 0
$0038
$0039 $003F
$FE00
Break Status Register Read: (BSR) Write: See page 161. Reset:
R
R
R
R
R
R
SBSW See note 1 0
R
1. Writing a 0 clears SBSW. SIM Reset Status Register Read: (SRSR) Write: See page 135. POR: POR 1 PIN 0 = Unimplemented COP 0 ILOP 0 R ILAD 0 = Reserved MODRST 0 U = Unaffected LVI 0 0 0
$FE01
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 5)
Data Sheet 26 Memory
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Memory Input/Output (I/O) Section
Addr. $FE02
Register Name Break Auxiliary Read: Register (BRKAR) Write: See page 160. Reset: Break Flag Control Read: Register (BFCR) Write: See page 161. Reset: Interrupt Status Register 1 Read: (INT1) Write: See page 77. Reset: Interrupt Status Register 2 Read: (INT2) Write: See page 77. Reset: Interrupt Status Register 3 Read: (INT3) Write: See page 77. Reset: Reserved FLASH Control Register Read: (FLCR) Write: See page 30. Reset: Break Address High Read: Register (BRKH) Write: See page 160. Reset: Break Address low Read: Register (BRKL) Write: See page 160. Reset: Break Status and Control Read: Register (BRKSCR) Write: See page 159. Reset: LVI Status Register Read: (LVISR) Write: See page 89. Reset: Reserved for FLASH Test
Bit 7 0 0 BCFE 0 0 R 0 IF14 R 0 0 R 0 R 0 0 Bit 15 0 Bit 7 0 BRKE 0 LVIOUT 0 R
6 0 0 R
5 0 0 R
4 0 0 R
3 0 0 R
2 0 0 R
1 0 0 R
Bit 0 BDCOP 0 R
$FE03
IF5 R 0 0 R 0 0 R 0 R 0 0 Bit 14 0 Bit 6 0 BRKA 0 0 0 R
IF4 R 0 0 R 0 0 R 0 R 0 0 Bit 13 0 Bit 5 0 0 0 0 0 R
IF3 R 0 0 R 0 0 R 0 R 0 0 Bit 12 0 Bit 4 0 0 0 0 0 R
0 R 0 0 R 0 0 R 0 R
IF1 R 0 0 R 0 0 R 0 R
0 R 0 0 R 0 0 R 0 R
0 R 0 0 R 0 IF15 R 0 R
$FE04
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$FE05
$FE06 $FE07
$FE08
HVEN 0 Bit 11 0 Bit 3 0 0 0 0 0 R
MASS 0 Bit 10 0 Bit 2 0 0 0 0 0 R
ERASE 0 Bit 9 0 Bit 1 0 0 0 0 0 R
PGM 0 Bit 8 0 Bit 0 0 0 0 R 0 R
$FE09
$FE0A
$FE0B
$FE0C $FE0D $FE0F
= Unimplemented
R
= Reserved
U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 5)
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Memory
Data Sheet 27
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Memory
Addr. $FFB0 $FFBD
Register Name Unimplemented
Bit 7
6
5
4
3
2
1
Bit 0
$FFBE $FFBF
FLASH Block Protect Read: Register (FLBPR) Write: See page 35. Reset: Unimplemented
BPR7 0
BPR6 0
BPR5 0
BPR4 0
BPR3 0
BPR2 0
BPR1 0
0 0
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Read: Internal Oscillator Trim Value Write: $FFC0 (Optional) Reset: $FFC1 $FFC2 $FFCF Reserved
TRIM7 1 R
TRIM6 0 R
TRIM5 0 R
TRIM4 0 R
TRIM3 0 R
TRIM2 0 R
TRIM1 0 R
TRIM0 0 R
Unimplemented
$FFFF
COP Control Register Read: (COPCTL) Write: See page 57. Reset:
LOW BYTE OF RESET VECTOR WRITING CLEARS COP COUNTER (ANY VALUE) Unaffected by reset = Unimplemented R = Reserved U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 5)
Data Sheet 28 Memory
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Memory Random-Access Memory (RAM)
Table 2-1 shows the MC68HC908QF4 reset and interrupt vectors.
.
Table 2-1. Vector Addresses
Vector Priority Lowest Vector IF14 $FFE1 IF13 IF6 IF5 -- $FFF2 Keyboard vector (low) Not used TIM overflow vector (high) TIM overflow vector (low) TIM channel 1 vector (high) TIM channel 1 vector (low) TIM channel 0 vector (high) TIM channel 0 vector (low) Not used IRQ vector (high) IRQ vector (low) SWI vector (high) SWI vector (low) Reset vector (high) Reset vector (low) Address $FFE0 Vector Keyboard vector (high)
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$FFF3 $FFF4 IF4 $FFF5 $FFF6 IF3 $FFF7 IF2 IF1 $FFFB $FFFC -- $FFFD $FFFE Highest -- $FFFF -- $FFFA
2.5 Random-Access Memory (RAM)
Addresses $0080-$00FF are RAM locations. The location of the stack RAM is programmable. The 16-bit stack pointer allows the stack to be anywhere in the 64-Kbyte memory space. NOTE: For correct operation, the stack pointer must point only to RAM locations. Before processing an interrupt, the central processor unit (CPU) uses five bytes of the stack to save the contents of the CPU registers. NOTE: For M6805, M146805, and M68HC05 compatibility, the H register is not stacked. During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls. NOTE: Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation.
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Memory
Data Sheet 29
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Memory
2.6 FLASH Memory (FLASH)
This subsection describes the operation of the embedded FLASH memory. The FLASH memory can be read, programmed, and erased from a single external supply. The program and erase operations are enabled through the use of an internal charge pump. The FLASH memory consists of an array of 4096 bytes with an additional 48 bytes for user vectors. The minimum size of FLASH memory that can be erased is 64 bytes; and the maximum size of FLASH memory that can be programmed in a program cycle is 32 bytes (a row). Program and erase operations are facilitated through control bits in the FLASH control register (FLCR). Details for these operations appear later in this section. The address ranges for the user memory and vectors are: * * NOTE: $EE00 - $FDFF; user memory, 4096 bytes $FFD0 - $FFFF; user interrupt vectors, 48 bytes.
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An erased bit reads as 1 and a programmed bit reads as 0. A security feature prevents viewing of the FLASH contents.(1)
2.6.1 FLASH Control Register The FLASH control register (FLCR) controls FLASH program and erase operations.
Address: Read: Write: Reset: 0 0 = Unimplemented 0 0 $FE08 Bit 7 0 6 0 5 0 4 0 3 HVEN 0 2 MASS 0 1 ERASE 0 Bit 0 PGM 0
Figure 2-3. FLASH Control Register (FLCR) HVEN -- High Voltage Enable Bit This read/write bit enables high voltage from the charge pump to the memory for either program or erase operation. It can only be set if either PGM =1 or ERASE =1 and the proper sequence for program or erase is followed. 1 = High voltage enabled to array and charge pump on 0 = High voltage disabled to array and charge pump off MASS -- Mass Erase Control Bit This read/write bit configures the memory for mass erase operation. 1 = Mass erase operation selected 0 = Mass erase operation unselected
1. No security feature is absolutely secure. However, Motorola's strategy is to make reading or copying the FLASH difficult for unauthorized users. Data Sheet 30 Memory MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Memory FLASH Memory (FLASH)
ERASE -- Erase Control Bit This read/write bit configures the memory for erase operation. ERASE is interlocked with the PGM bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = Erase operation selected 0 = Erase operation unselected PGM -- Program Control Bit This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = Program operation selected 0 = Program operation unselected 2.6.2 FLASH Page Erase Operation Use the following procedure to erase a page of FLASH memory. A page consists of 64 consecutive bytes starting from addresses $XX00, $XX40, $XX80, or $XXC0. The 48-byte user interrupt vectors area also forms a page. Any FLASH memory page can be erased alone. 1. Set the ERASE bit and clear the MASS bit in the FLASH control register. 2. Read the FLASH block protect register. 3. Write any data to any FLASH location within the address range of the block to be erased. 4. Wait for a time, tNVS (minimum 10 s). 5. Set the HVEN bit. 6. Wait for a time, tErase (minimum 1 ms or 4 ms). 7. Clear the ERASE bit. 8. Wait for a time, tNVH (minimum 5 s). 9. Clear the HVEN bit. 10. After time, tRCV (typical 1 s), the memory can be accessed in read mode again. Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. In applications that need up to 10,000 program/erase cycles, use the 4 ms page erase specification to get improved long-term reliability. Any application can use this 4 ms page erase specification. However, in applications where a FLASH location will be erased and reprogrammed less than 1000 times, and speed is important, use the 1 ms page erase specification to get a lower minimum erase time.
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NOTE:
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Memory
Data Sheet 31
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Memory
2.6.3 FLASH Mass Erase Operation Use the following procedure to erase the entire FLASH memory to read as 1: 1. Set both the ERASE bit and the MASS bit in the FLASH control register. 2. Read from the FLASH block protect register. 3. Write any data to any FLASH address(1) within the FLASH memory address range. 4. Wait for a time, tNVS (minimum 10 s). 5. Set the HVEN bit. 6. Wait for a time, tErase (minimum 4 ms). 7. Clear the ERASE and MASS bits.
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NOTE:
Mass erase is disabled whenever any block is protected (FLBPR does not equal $FF). 8. Wait for a time, tNVH1 (minimum 100 s). 9. Clear the HVEN bit. 10. After time, tRCV (typical 1 s), the memory can be accessed in read mode again.
NOTE:
Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps.
2.6.4 FLASH Program Operation Programming of the FLASH memory is done on a row basis. A row consists of 32 consecutive bytes starting from addresses $XX00, $XX20, $XX40, $XX60, $XX80, $XXA0, $XXC0, or $XXE0. Use the following step-by-step procedure to program a row of FLASH memory Figure 2-4 shows a flowchart of the programming algorithm. NOTE: Only bytes which are currently $FF may be programmed. 1. Set the PGM bit. This configures the memory for program operation and enables the latching of address and data for programming. 2. Read from the FLASH block protect register. 3. Write any data to any FLASH location within the address range desired. 4. Wait for a time, tNVS (minimum 10 s). 5. Set the HVEN bit. 6. Wait for a time, tPGS (minimum 5 s).
1. When in monitor mode, with security sequence failed (see 16.3.2 Security), write to the FLASH block protect register instead of any FLASH address. Data Sheet 32 Memory MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Memory FLASH Memory (FLASH)
7. 8. 9. 10. 11. 12. 13. NOTE:
Write data to the FLASH address being programmed(1). Wait for time, tPROG (minimum 30 s). Repeat step 7 and 8 until all desired bytes within the row are programmed. Clear the PGM bit(1). Wait for time, tNVH (minimum 5 s). Clear the HVEN bit. After time, tRCV (typical 1 s), the memory can be accessed in read mode again.
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The COP register at location $FFFF should not be written between steps 5-12, when the HVEN bit is set. Since this register is located at a valid FLASH address, unpredictable behavior may occur if this location is written while HVEN is set. This program sequence is repeated throughout the memory until all data is programmed.
NOTE:
Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order shown, other unrelated operations may occur between the steps. Do not exceed tPROG maximum, see 17.12 Memory Characteristics.
2.6.5 FLASH Protection Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target application, provision is made to protect blocks of memory from unintentional erase or program operations due to system malfunction. This protection is done by use of a FLASH block protect register (FLBPR). The FLBPR determines the range of the FLASH memory which is to be protected. The range of the protected area starts from a location defined by FLBPR and ends to the bottom of the FLASH memory ($FFFF). When the memory is protected, the HVEN bit cannot be set in either ERASE or PROGRAM operations. NOTE: In performing a program or erase operation, the FLASH block protect register must be read after setting the PGM or ERASE bit and before asserting the HVEN bit. When the FLBPR is programmed with all 0 s, the entire memory is protected from being programmed and erased. When all the bits are erased (all 1's), the entire memory is accessible for program and erase.
1. The time between each FLASH address change, or the time between the last FLASH address programmed to clearing PGM bit, must not exceed the maximum programming time, tPROG maximum. MC68HC908QF4 -- Rev. 1.0 MOTOROLA Memory Data Sheet 33
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Algorithm for Programming a Row (32 Bytes) of FLASH Memory
1
SET PGM BIT
2 READ THE FLASH BLOCK PROTECT REGISTER
3
WRITE ANY DATA TO ANY FLASH ADDRESS WITHIN THE ROW ADDRESS RANGE DESIRED
4
WAIT FOR A TIME, tnvs
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5
SET HVEN BIT
6
WAIT FOR A TIME, tpgs
7
WRITE DATA TO THE FLASH ADDRESS TO BE PROGRAMMED
8
WAIT FOR A TIME, tPROG
9
COMPLETED PROGRAMMING THIS ROW? N
Y
10
CLEAR PGM BIT
11
WAIT FOR A TIME, tnvh
12
CLEAR HVEN BIT
Notes: The time between each FLASH address change (step 6 to step 9), or the time between the last FLASH address programmed to clearing PGM bit (step 6 to step 9) must not exceed the maximum programming time, tPROG, maximum. This row program algorithm assumes the row/s to be programmed are initially erased.
13
WAIT FOR A TIME, trcv
END OF PROGRAMMING
Figure 2-4. FLASH Programming Flowchart
Data Sheet 34 Memory
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Memory FLASH Memory (FLASH)
When bits within the FLBPR are programmed, they lock a block of memory. The address ranges are shown in 2.6.6 FLASH Block Protect Register. Once the FLBPR is programmed with a value other than $FF, any erase or program of the FLBPR or the protected block of FLASH memory is prohibited. Mass erase is disabled whenever any block is protected (FLBPR does not equal $FF). The FLBPR itself can be erased or programmed only with an external voltage, VTST, present on the IRQ pin. This voltage also allows entry from reset into the monitor mode. 2.6.6 FLASH Block Protect Register
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The FLASH block protect register is implemented as a byte within the FLASH memory, and therefore can only be written during a programming sequence of the FLASH memory. The value in this register determines the starting address of the protected range within the FLASH memory.
Address: $FFBE Bit 7 Read: BPR7 Write: Reset: U U U U U U U U BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0 6 5 4 3 2 1 Bit 0
U = Unaffected by reset. Initial value from factory is 1. Write to this register is by a programming sequence to the FLASH memory.
Figure 2-5. FLASH Block Protect Register (FLBPR) BPR[7:0] -- FLASH Protection Register Bits [7:0] These eight bits in FLBPR represent bits [13:6] of a 16-bit memory address. Bits [15:14] are 1s and bits [5:0] are 0s. The resultant 16-bit address is used for specifying the start address of the FLASH memory for block protection. The FLASH is protected from this start address to the end of FLASH memory, at $FFFF. With this mechanism, the protect start address can be XX00, XX40, XX80, or XXC0 within the FLASH memory. See Figure 2-6 and Table 2-2.
16-BIT MEMORY ADDRESS START ADDRESS OF FLASH BLOCK PROTECT 1 1 FLBPR VALUE 0 0 0 0 0 0
Figure 2-6. FLASH Block Protect Start Address
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Memory
Data Sheet 35
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Table 2-2. Examples of Protect Start Address
BPR[7:0] $00-$B8 $B9 (1011 1001) $BA (1011 1010) $BB (1011 1011) $BC (1011 1100) Start of Address of Protect Range The entire FLASH memory is protected. $EE40 (1110 1110 0100 0000) $EE80 (1110 1110 1000 0000) $EEC0 (1110 1110 1100 0000) $EF00 (1110 1111 0000 0000) and so on... $DE (1101 1110) $F780 (1111 0111 1000 0000) $F7C0 (1111 0111 1100 0000) $FF80 (1111 1111 1000 0000) FLBPR, OSCTRIM, and vectors are protected The entire FLASH memory is not protected.
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$DF (1101 1111) $FE (1111 1110) $FF
2.6.7 Wait Mode Putting the MCU into wait mode while the FLASH is in read mode does not affect the operation of the FLASH memory directly, but there will not be any memory activity since the CPU is inactive. The WAIT instruction should not be executed while performing a program or erase operation on the FLASH, or the operation will discontinue and the FLASH will be on standby mode. 2.6.8 Stop Mode Putting the MCU into stop mode while the FLASH is in read mode does not affect the operation of the FLASH memory directly, but there will not be any memory activity since the CPU is inactive. The STOP instruction should not be executed while performing a program or erase operation on the FLASH, or the operation will discontinue and the FLASH will be on standby mode NOTE: Standby mode is the power-saving mode of the FLASH module in which all internal control signals to the FLASH are inactive and the current consumption of the FLASH is at a minimum.
Data Sheet 36 Memory
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Data Sheet -- MC68HC908QF4
Section 3. Analog-to-Digital Converter (ADC)
3.1 Introduction
This section describes the analog-to-digital converter (ADC). The ADC is an 8-bit, 4-channel analog-to-digital converter.
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3.2 Features
Features of the ADC module include: * * * * * * 4 channels with multiplexed input Linear successive approximation with monotonicity 8-bit resolution Single or continuous conversion Conversion complete flag or conversion complete interrupt Selectable ADC clock frequency
Figure 3-1 provides a summary of the input/output (I/O) registers.
Addr. $003C $003D Register Name ADC Status and Control Register (ADSCR) See page 42. Unimplemented Read: Write: Reset: Read: Write: Reset: ADIV2 0 ADIV1 0 = Unimplemented ADIV0 0 Read: Write: Reset: 0 Bit 7 COCO 6 AIEN 0 5 ADCO 0 4 CH4 1 3 CH3 1 2 CH2 1 1 CH1 1 Bit 0 CH0 1
$003E
ADC Data Register (ADR) See page 43. ADC Input Clock Register (ADICLK) See page 44.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Indeterminate after reset 0 0 0 0 0 0 0 0 0 0
$003F
Figure 3-1. ADC I/O Register Summary
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Analog-to-Digital Converter (ADC)
Data Sheet 37
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Analog-to-Digital Converter (ADC)
PTA0/AD0/TCH0/KBI0 PTA1/AD1/TCH1/KBI1 DDRA PTA PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 M68HC08 CPU PTB0 PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 CLOCK GENERATOR (OSCILLATOR)
SYSTEM INTEGRATION MODULE SINGLE INTERRUPT MODULE BREAK MODULE POWER-ON RESET MODULE KEYBOARD INTERRUPT MODULE 16-BIT TIMER MODULE COP MODULE VCC MODE PLLEN DATA BS OP1 GND REXT XTAL1 XTAL0 UPCLK PFD
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8-BIT ADC
DDRB
PTB
MC68HC908QF4 4096 BYTES USER FLASH
128 BYTES RAM
MONITOR ROM
UHF TRANSMITTER
VDD POWER SUPPLY VSS
RST, IRQ: Pins have internal (about 30K Ohms) pull up PTA[0:5]: High current sink and source capability PTA[0:5]: Pins have programmable keyboard interrupt and pull up
Figure 3-2. Block Diagram Highlighting ADC Block and Pins
Data Sheet 38 Analog-to-Digital Converter (ADC)
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Analog-to-Digital Converter (ADC) Functional Description
3.3 Functional Description
Four ADC channels are available for sampling external sources at pins PTA0, PTA1, PTA4, and PTA5. An analog multiplexer allows the single ADC converter to select one of the four ADC channels as an ADC voltage input (ADCVIN). ADCVIN is converted by the successive approximation register-based counters. The ADC resolution is eight bits. When the conversion is completed, ADC puts the result in the ADC data register and sets a flag or generates an interrupt. Figure 3-3 shows a block diagram of the ADC.
INTERNAL DATA BUS READ DDRA DISABLE RESET WRITE PTA PTAx ADCx DDRAx
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WRITE DDRA
READ PTA
DISABLE ADC CHANNEL x ADC DATA REGISTER
INTERRUPT LOGIC
CONVERSION COMPLETE
ADC VOLTAGE IN ADCVIN ADC
CHANNEL SELECT (1 OF 4 CHANNELS)
CH[4:0]
AIEN
COCO
ADC CLOCK
BUS CLOCK
CLOCK GENERATOR
ADIV[2:0]
Figure 3-3. ADC Block Diagram
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Analog-to-Digital Converter (ADC)
Data Sheet 39
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Analog-to-Digital Converter (ADC)
3.3.1 ADC Port I/O Pins PTA0, PTA1, PTA4, and PTA5 are general-purpose I/O pins that are shared with the ADC channels. The channel select bits (ADC status and control register (ADSCR), $003C), define which ADC channel/port pin will be used as the input signal. The ADC overrides the port I/O logic by forcing that pin as input to the ADC. The remaining ADC channels/port pins are controlled by the port I/O logic and can be used as general-purpose I/O. Writes to the port register or data direction register (DDR) will not have any affect on the port pin that is selected by the ADC. Read of a port pin which is in use by the ADC will return a 0 if the corresponding DDR bit is at 0. If the DDR bit is 1, the value in the port data latch is read.
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3.3.2 Voltage Conversion When the input voltage to the ADC equals VDD, the ADC converts the signal to $FF (full scale). If the input voltage equals VSS, the ADC converts it to $00. Input voltages between VDD and VSS are a straight-line linear conversion. All other input voltages will result in $FF if greater than VDD and $00 if less than VSS. NOTE: Input voltage should not exceed the analog supply voltages.
3.3.3 Conversion Time Sixteen ADC internal clocks are required to perform one conversion. The ADC starts a conversion on the first rising edge of the ADC internal clock immediately following a write to the ADSCR. If the ADC internal clock is selected to run at 1 MHz, then one conversion will take 16 s to complete. With a 1-MHz ADC internal clock the maximum sample rate is 62.5 kHz.
Conversion Time = 16 ADC Clock Cycles ADC Clock Frequency Number of Bus Cycles = Conversion Time x Bus Frequency
3.3.4 Continuous Conversion In the continuous conversion mode (ADCO = 1), the ADC continuously converts the selected channel filling the ADC data register (ADR) with new data after each conversion. Data from the previous conversion will be overwritten whether that data has been read or not. Conversions will continue until the ADCO bit is cleared. The COCO bit (ADSCR, $003C) is set after each conversion and will stay set until the next read of the ADC data register. When a conversion is in process and the ADSCR is written, the current conversion data should be discarded to prevent an incorrect reading. 3.3.5 Accuracy and Precision The conversion process is monotonic and has no missing codes.
Data Sheet 40 Analog-to-Digital Converter (ADC) MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Analog-to-Digital Converter (ADC) Interrupts
3.4 Interrupts
When the AIEN bit is set, the ADC module is capable of generating a central processor unit (CPU) interrupt after each ADC conversion. A CPU interrupt is generated if the COCO bit is at 0. The COCO bit is not used as a conversion complete flag when interrupts are enabled.
3.5 Low-Power Modes
The following subsections describe the ADC in low-power modes.
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3.5.1 Wait Mode The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC can bring the microcontroller unit (MCU) out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power down the ADC by setting the CH[4:0] bits in ADSCR to 1s before executing the WAIT instruction. 3.5.2 Stop Mode The ADC module is inactive after the execution of a STOP instruction. Any pending conversion is aborted. ADC conversions resume when the MCU exits stop mode. Allow one conversion cycle to stabilize the analog circuitry before using ADC data after exiting stop mode.
3.6 Input/Output Signals
The ADC module has four channels that are shared with I/O port A. ADC voltage in (ADCVIN) is the input voltage signal from one of the four ADC channels to the ADC module.
3.7 Input/Output Registers
These I/O registers control and monitor ADC operation: * * * ADC status and control register (ADSCR) ADC data register (ADR) ADC clock register (ADICLK)
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Analog-to-Digital Converter (ADC)
Data Sheet 41
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Analog-to-Digital Converter (ADC)
3.7.1 ADC Status and Control Register The following paragraphs describe the function of the ADC status and control register (ADSCR). When a conversion is in process and the ADSCR is written, the current conversion data should be discarded to prevent an incorrect reading.
Address: $003C Bit 7 Read: Write: COCO AIEN ADCO 0 CH4 1 CH3 1 CH2 1 CH1 1 CH0 1 6 5 4 3 2 1 Bit 0
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Reset:
0
0
= Unimplemented
Figure 3-4. ADC Status and Control Register (ADSCR) COCO -- Conversions Complete Bit In non-interrupt mode (AIEN = 0), COCO is a read-only bit that is set at the end of each conversion. COCO will stay set until cleared by a read of the ADC data register. Reset clears this bit. In interrupt mode (AIEN = 1), COCO is a read-only bit that is not set at the end of a conversion. It always reads as a 0. 1 = Conversion completed (AIEN = 0) 0 = Conversion not completed (AIEN = 0) or CPU interrupt enabled (AIEN = 1) NOTE: The write function of the COCO bit is reserved. When writing to the ADSCR register, always have a 0 in the COCO bit position. AIEN -- ADC Interrupt Enable Bit When this bit is set, an interrupt is generated at the end of an ADC conversion. The interrupt signal is cleared when ADR is read or ADSCR is written. Reset clears the AIEN bit. 1 = ADC interrupt enabled 0 = ADC interrupt disabled ADCO -- ADC Continuous Conversion Bit When set, the ADC will convert samples continuously and update ADR at the end of each conversion. Only one conversion is allowed when this bit is cleared. Reset clears the ADCO bit. 1 = Continuous ADC conversion 0 = One ADC conversion CH[4:0] -- ADC Channel Select Bits CH4, CH3, CH2, CH1, and CH0 form a 5-bit field which is used to select one of the four ADC channels. The five select bits are detailed in Table 3-1. Care
Data Sheet 42 Analog-to-Digital Converter (ADC)
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Analog-to-Digital Converter (ADC) Input/Output Registers
should be taken when using a port pin as both an analog and a digital input simultaneously to prevent switching noise from corrupting the analog signal. The ADC subsystem is turned off when the channel select bits are all set to 1. This feature allows for reduced power consumption for the MCU when the ADC is not used. Reset sets all of these bits to a 1. NOTE: Recovery from the disabled state requires one conversion cycle to stabilize. Table 3-1. MUX Channel Select
CH4 CH3 0 0 0 0 0 1 1 1 1 1 1 CH2 0 0 0 0 1 0 0 1 1 1 1 CH1 0 0 1 1 0 1 1 0 0 1 1 CH0 0 1 0 1 0 0 1 0 1 0 1 ADC Channel AD0 AD1 AD2 AD3 -- -- -- -- -- -- -- -- Reserved Unused VDDA(2) VSSA(2) ADC power off Unused(1) Input Select PTA0 PTA1 PTA4 PTA5
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0 0 0 0 0 1 1 1 1 1 1
1. If any unused channels are selected, the resulting ADC conversion will be unknown. 2. The voltage levels supplied from internal reference nodes, as specified in the table, are used to verify the operation of the ADC converter both in production test and for user applications.
3.7.2 ADC Data Register One 8-bit result register is provided. This register is updated each time an ADC conversion completes.
Address: $003E Bit 7 Read: Bit 7 Write: Reset: Indeterminate after reset Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 6 5 4 3 2 1 Bit 0
Figure 3-5. ADC Data Register (ADR)
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Analog-to-Digital Converter (ADC)
Data Sheet 43
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Analog-to-Digital Converter (ADC)
3.7.3 ADC Input Clock Register This register selects the clock frequency for the ADC.
Address: $003F Bit 7 Read: ADIV2 Write: Reset: 0 0 0 0 0 0 0 0 ADIV1 ADIV0 6 5 4 0 3 0 2 0 1 0 Bit 0 0
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= Unimplemented
Figure 3-6. ADC Input Clock Register (ADICLK) ADIV2-ADIV0 -- ADC Clock Prescaler Bits ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate the internal ADC clock. Table 3-2 shows the available clock configurations. The ADC clock should be set according to the MCU operating voltage. Lower operating voltages will require lower ADC clock frequencies for best accuracy. The analog input level should remain stable for the entire conversion time (maximum = 17 ADC clock cycles). Table 3-2. ADC Clock Divide Ratio
ADIV2 0 0 0 0 1 X = don't care ADIV1 0 0 1 1 X ADIV0 0 1 0 1 X ADC Clock Rate Bus clock / 1 Bus clock / 2 Bus clock / 4 Bus clock / 8 Bus clock / 16
Data Sheet 44 Analog-to-Digital Converter (ADC)
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Data Sheet -- MC68HC908QF4
Section 4. Auto Wakeup Module (AWU)
4.1 Introduction
This section describes the auto wakeup module (AWU). The AWU generates a periodic interrupt during stop mode to wake the part up without requiring an external signal. Figure 4-2 is a block diagram of the AWU.
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4.2 Features
Features of the auto wakeup module include: * * * * One internal interrupt with separate interrupt enable bit, sharing the same keyboard interrupt vector and keyboard interrupt mask bit Exit from low-power stop mode without external signals Selectable timeout periods Dedicated low power internal oscillator separate from the main system clock sources
Figure 4-1 provides a summary of the input/output (I/O) registers used in conjuction with the AWU.
Addr.
Register Name Read: Port A Data Register (PTA) Write: See page 48. Reset: Keyboard Status Read: and Control Register Write: (KBSCR) See page 48. Reset: Read: Keyboard Interrupt Enable Register (KBIER) Write: See page 49. Reset:
Bit 7 0
6 AWUL
5 PTA5
4 PTA4
3 PTA3
2 PTA2
1 PTA1
Bit 0 PTA0
$0000
Unaffected by reset 0 0 0 0 KEYF 0 IMASKK ACKK 0 0 AWUIE 0 0 = Unimplemented KBIE5 0 KBIE4 0 KBIE3 0 KBIE2 0 KBIE1 0 KBIE0 0 0 0 0 0 0 0 0 MODEK
$001A
$001B
Figure 4-1. AWU Register Summary
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Auto Wakeup Module (AWU)
Data Sheet 45
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Auto Wakeup Module (AWU)
4.3 Functional Description
The function of the auto wakeup logic is to generate periodic wakeup requests to bring the microcontroller unit (MCU) out of stop mode. The wakeup requests are treated as regular keyboard interrupt requests, with the difference that instead of a pin, the interrupt signal is generated by an internal logic. Writing the AWUIE bit in the keyboard interrupt enable register enables or disables the auto wakeup interrupt input (see Figure 4-2). A logic 1 applied to the AWUIREQ input with auto wakeup interrupt request enabled, latches an auto wakeup interrupt request.
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Auto wakeup latch, AWUL, can be read directly from the bit 6 position of port A data register (PTA). This is a read-only bit which is occupying an empty bit position on PTA. No PTA associated registers, such as PTA6 data direction or PTA6 pullup exist for this bit. Entering stop mode will enable the auto wakeup generation logic. An internal RC oscillator (exclusive for the auto wakeup feature) drives the wakeup request generator. Once the overflow count is reached in the generator counter, a wakeup request, AWUIREQ, is latched and sent to the KBI logic. See Figure 4-1. Wakeup interrupt requests will only be serviced if the associated interrupt enable bit, AWUIE, in KBIER is set. The AWU shares the keyboard interrupt vector.
COPRS (FROM CONFIG1) AUTOWUGEN 1 = DIV 29 SHORT 0 = DIV 214 INT RC OSC EN 32 kHz CLK OVERFLOW RST VDD TO PTA READ, BIT 6 D Q AWUL
E
AWUIREQ R TO KBI INTERRUPT LOGIC (SEE Figure 9-3. Keyboard Interrupt Block Diagram)
CLRLOGIC CLEAR (CGMXCLK) BUSCLKX4 CLK RST RESET ISTOP RESET ACKK
RESET AWUIE
Figure 4-2. Auto Wakeup Interrupt Request Generation Logic
Data Sheet 46 Auto Wakeup Module (AWU)
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Auto Wakeup Module (AWU) Wait Mode
The overflow count can be selected from two options defined by the COPRS bit in CONFIG1. This bit was "borrowed" from the computer operating properly (COP) using the fact that the COP feature is idle (no MCU clock available) in stop mode. The typical values of the periodic wakeup request are (at room temperature): * * COPRS = 0: 875 ms @ 3.0 V, 1.1 s @ 2.3 V COPRS = 1: 22 ms @ 3.0 V, 27 ms @ 2.3 V
The auto wakeup RC oscillator is highly dependent on operating voltage and temperature. This feature is not recommended for use as a time-keeping function. The wakeup request is latched to allow the interrupt source identification. The latched value, AWUL, can be read directly from the bit 6 position of PTA data register. This is a read-only bit which is occupying an empty bit position on PTA. No PTA associated registers, such as PTA6 data, PTA6 direction, and PTA6 pullup exist for this bit. The latch can be cleared by writing to the ACKK bit in the KBSCR register. Reset also clears the latch. AWUIE bit in KBI interrupt enable register (see Figure 4-2) has no effect on AWUL reading. The AWU oscillator and counters are inactive in normal operating mode and become active only upon entering stop mode.
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4.4 Wait Mode
The AWU module remains inactive in wait mode.
4.5 Stop Mode
When the AWU module is enabled (AWUIE = 1 in the keyboard interrupt enable register) it is activated automatically upon entering stop mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode. The AWU counters start from `0' each time stop mode is entered.
4.6 Input/Output Registers
The AWU shares registers with the keyboard interrupt (KBI) module and the port A I/O module. The following I/O registers control and monitor operation of the AWU: * * * Port A data register (PTA) Keyboard interrupt status and control register (KBSCR) Keyboard interrupt enable register (KBIER)
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Auto Wakeup Module (AWU)
Data Sheet 47
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Auto Wakeup Module (AWU)
4.6.1 Port A I/O Register The port A data register (PTA) contains a data latch for the state of the AWU interrupt request, in addition to the data latches for port A.
Address: $0000 Bit 7 Read: Write: Reset: 0 0 = Unimplemented 0 6 AWUL 5 PTA5 4 PTA4 3 PTA3 2 PTA2 1 PTA1 Bit 0 PTA0
Unaffected by reset
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Figure 4-3. Port A Data Register (PTA) AWUL -- Auto Wakeup Latch This is a read-only bit which has the value of the auto wakeup interrupt request latch. The wakeup request signal is generated internally. There is no PTA6 port or any of the associated bits such as PTA6 data direction or pullup bits. 1 = Auto wakeup interrupt request is pending 0 = Auto wakeup interrupt request is not pending NOTE: PTA5-PTA0 bits are not used in conjuction with the auto wakeup feature. To see a description of these bits, see 13.2.1 Port A Data Register.
4.6.2 Keyboard Status and Control Register The keyboard status and control register (KBSCR): * * * Flags keyboard/auto wakeup interrupt requests Acknowledges keyboard/auto wakeup interrupt requests Masks keyboard/auto wakeup interrupt requests
Address: $001A Bit 7 Read: Write: Reset: 0 0 0 0 0 = Unimplemented 0 6 0 5 0 4 0 3 KEYF 2 0 ACKK 0 1 IMASKK 0 Bit 0 MODEK 0
Figure 4-4. Keyboard Status and Control Register (KBSCR) Bits 7-4 -- Not used These read-only bits always read as 0s. KEYF -- Keyboard Flag Bit This read-only bit is set when a keyboard interrupt is pending on port A or auto wakeup. Reset clears the KEYF bit. 1 = Keyboard/auto wakeup interrupt pending 0 = No keyboard/auto wakeup interrupt pending
Data Sheet 48 Auto Wakeup Module (AWU)
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Auto Wakeup Module (AWU) Input/Output Registers
ACKK -- Keyboard Acknowledge Bit Writing a 1 to this write-only bit clears the keyboard/auto wakeup interrupt request on port A and auto wakeup logic. ACKK always reads as 0. Reset clears ACKK. IMASKK-- Keyboard Interrupt Mask Bit Writing a 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests on port A or auto wakeup. Reset clears the IMASKK bit. 1 = Keyboard/auto wakeup interrupt requests masked 0 = Keyboard/auto wakeup interrupt requests not masked
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NOTE:
MODEK is not used in conjuction with the auto wakeup feature. To see a description of this bit, see 9.7.1 Keyboard Status and Control Register.
4.6.3 Keyboard Interrupt Enable Register The keyboard interrupt enable register (KBIER) enables or disables the auto wakeup to operate as a keyboard/auto wakeup interrupt input.
Address: $001B Bit 7 Read: Write: Reset: 0 0 6 AWUIE 0 5 KBIE5 0 4 KBIE4 0 3 KBIE3 0 2 KBIE2 0 1 KBIE1 0 Bit 0 KBIE0 0
= Unimplemented
Figure 4-5. Keyboard Interrupt Enable Register (KBIER) AWUIE -- Auto Wakeup Interrupt Enable Bit This read/write bit enables the auto wakeup interrupt input to latch interrupt requests. Reset clears AWUIE. 1 = Auto wakeup enabled as interrupt input 0 = Auto wakeup not enabled as interrupt input NOTE: KBIE5-KBIE0 bits are not used in conjuction with the auto wakeup feature. To see a description of these bits, see 9.7.2 Keyboard Interrupt Enable Register.
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Auto Wakeup Module (AWU)
Data Sheet 49
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Auto Wakeup Module (AWU)
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Data Sheet 50 Auto Wakeup Module (AWU)
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Data Sheet -- MC68HC908QF4
Section 5. Configuration Register (CONFIG)
5.1 Introduction
This section describes the configuration registers (CONFIG1 and CONFIG2). The configuration registers enable or disable the following options: *
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Stop mode recovery time (32 x BUSCLKX4 cycles or 4096 x BUSCLKX4 cycles) STOP instruction Computer operating properly module (COP) COP reset period (COPRS): (213 -24) x BUSCLKX4 or (218 -24) x BUSCLKX4 Low-voltage inhibit (LVI) enable and trip voltage selection OSC option selection IRQ pin RST pin Auto wakeup timeout period
* * * * * * * *
5.2 Functional Description
The configuration registers are used in the initialization of various options. The configuration registers can be written once after each reset. Exceptions are bits LVDLVR and LVIRSTD which may be written at any time. Most of the configuration register bits are cleared during reset. Since the various options affect the operation of the microcontroller unit (MCU) it is recommended that this register be written immediately after reset. The configuration registers are located at $001E and $001F, and may be read at anytime.
Address: $001E Bit 7 Read: Write: Reset: POR: IRQPUD 0 0 R 6 IRQEN 0 0 = Reserved 5 R 0 0 4 OSCOPT1 0 0 U = Unaffected 3 OSCOPT0 0 0 2 R 0 0 1 R 0 0 Bit 0 RSTEN U 0
Figure 5-1. Configuration Register 2 (CONFIG2)
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Configuration Register (CONFIG)
Data Sheet 51
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Configuration Register (CONFIG)
IRQPUD -- IRQ Pin Pullup Control Bit 1 = Internal pullup is disconnected 0 = Internal pullup is connected between IRQ pin and VDD IRQEN -- IRQ Pin Function Selection Bit 1 = Interrupt request function active in pin 0 = Interrupt request function inactive in pin OSCOPT1 and OSCOPT0 -- Selection Bits for Oscillator Option (0, 0) Internal oscillator (0, 1) External oscillator (1, 0) External RC oscillator (1, 1) External XTAL oscillator
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RSTEN -- RST Pin Function Selection 1 = Reset function active in pin 0 = Reset function inactive in pin NOTE: The RSTEN bit is cleared by a power-on reset (POR) only. Other resets will leave this bit unaffected.
Address: $001F Bit 7 Read: Write: Reset: 6 5 LVIRSTD 0 0 4 3 2 1 Bit 0
COPRS
0 0
LVISTOP
0 0
LVIPWRD LVDLVR
0 0 U 0
SSREC
0 0
STOP
0 0
COPD
0 0
POR:
U = Unaffected
Figure 5-2. Configuration Register 1 (CONFIG1) COPRS (Out of STOP Mode) -- COP Reset Period Selection Bit 1 = COP reset short cycle = (213 - 24) x BUSCLKX4 0 = COP reset long cycle = (218 - 24) x BUSCLKX4 COPRS (In STOP Mode) -- Auto Wakeup Period Selection Bit 1 = Auto wakeup short cycle = (29) x INTRCOSC 0 = Auto wakeup long cycle = (214) x INTRCOSC LVISTOP -- LVI Enable in Stop Mode Bit When the LVIPWRD bit is clear, setting the LVISTOP bit enables the LVI to operate during stop mode. Reset clears LVISTOP. 1 = LVI enabled during stop mode 0 = LVI disabled during stop mode
Data Sheet 52 Configuration Register (CONFIG)
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Configuration Register (CONFIG) Functional Description
LVIRSTD -- LVI Reset Disable Bit LVIRSTD disables the reset signal from the LVI module. Unlike other configuration bits, the LVIRSTD can be written at any time. 1 = LVI module resets disabled 0 = LVI module resets enabled LVIPWRD -- LVI Power Disable Bit LVIPWRD disables the LVI module. 1 = LVI module power disabled 0 = LVI module power enabled LVDLVR -- Low Voltage Detect or Low Voltage Reset Mode Bit LVDLVR selects the trip voltage of the LVI module. LVD trip voltage can be used as a low voltage warning, while LVR will commonly be used as a reset condition. Unlike other CONFIG bits, LVDLVR can be written multiple times after reset. 1 = LVI trip voltage level set to LVD trip voltage 0 = LVI trip voltage level set to LVR trip voltage NOTE: The LVDLVR bit is cleared by a power-on reset (POR) only. Other resets will leave this bit unaffected. SSREC -- Short Stop Recovery Bit SSREC enables the CPU to exit stop mode with a delay of 32 BUSCLKX4 cycles instead of a 4096 BUSCLKX4 cycle delay. 1 = Stop mode recovery after 32 BUSCLKX4 cycles 0 = Stop mode recovery after 4096 BUSCLKX4 cycles NOTE: Exiting stop mode by an LVI reset will result in the long stop recovery. When using the LVI during normal operation but disabling during stop mode, the LVI will have an enable time of tEN. The system stabilization time for power-on reset and long stop recovery (both 4096 BUSCLKX4 cycles) gives a delay longer than the LVI enable time for these startup scenarios. There is no period where the MCU is not protected from a low-power condition. However, when using the short stop recovery configuration option, the 32 BUSCLKX4 delay must be greater than the LVI's turn on time to avoid a period in startup where the LVI is not protecting the MCU. STOP -- STOP Instruction Enable Bit STOP enables the STOP instruction. 1 = STOP instruction enabled 0 = STOP instruction treated as illegal opcode COPD -- COP Disable Bit COPD disables the COP module. 1 = COP module disabled 0 = COP module enabled
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MC68HC908QF4 -- Rev. 1.0 MOTOROLA Configuration Register (CONFIG)
Data Sheet 53
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Configuration Register (CONFIG)
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Data Sheet 54 Configuration Register (CONFIG)
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Data Sheet -- MC68HC908QF4
Section 6. Computer Operating Properly (COP)
6.1 Introduction
The computer operating properly (COP) module contains a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset by clearing the COP counter periodically. The COP module can be disabled through the COPD bit in the configuration 1 (CONFIG1) register.
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6.2 Functional Description
BUSCLKX4
12-BIT SIM COUNTER CLEAR ALL STAGES CLEAR STAGES 5-12
RESET CIRCUIT RESET STATUS REGISTER
STOP INSTRUCTION INTERNAL RESET SOURCES COPCTL WRITE
COP CLOCK
COPEN (FROM SIM) COP DISABLE (FROM CONFIG1) RESET COPCTL WRITE COP RATE SELECT (COPRS FROM CONFIG1)
6-BIT COP COUNTER
CLEAR COP COUNTER
Figure 6-1. COP Block Diagram
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Computer Operating Properly (COP)
COP TIMEOUT
Data Sheet 55
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Computer Operating Properly (COP)
The COP counter is a free-running 6-bit counter preceded by the 12-bit system integration module (SIM) counter. If not cleared by software, the COP counter overflows and generates an asynchronous reset after 218 - 24 or 213 - 24 BUSCLKX4 cycles; depending on the state of the COP rate select bit, COPRS, in configuration register 1. With a 218 - 24 BUSCLKX4 cycle overflow option, the internal 12.8-MHz oscillator gives a COP timeout period of 20.48 ms. Writing any value to location $FFFF before an overflow occurs prevents a COP reset by clearing the COP counter and stages 12-5 of the SIM counter. NOTE: Service the COP immediately after reset and before entering or after exiting stop mode to guarantee the maximum time before the first COP counter overflow. A COP reset pulls the RST pin low (if the RSTEN bit is set in the CONFIG1 register) for 32 x BUSCLKX4 cycles and sets the COP bit in the reset status register (RSR). See 14.8.1 SIM Reset Status Register. NOTE: Place COP clearing instructions in the main program and not in an interrupt subroutine. Such an interrupt subroutine could keep the COP from generating a reset even while the main program is not working properly.
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6.3 I/O Signals
The following paragraphs describe the signals shown in Figure 6-1. 6.3.1 BUSCLKX4 BUSCLKX4 is the oscillator output signal. BUSCLKX4 frequency is equal to the crystal frequency or the RC-oscillator frequency. 6.3.2 STOP Instruction The STOP instruction clears the SIM counter. 6.3.3 COPCTL Write Writing any value to the COP control register (COPCTL) (see 6.4 COP Control Register) clears the COP counter and clears stages 12-5 of the SIM counter. Reading the COP control register returns the low byte of the reset vector. 6.3.4 Power-On Reset The power-on reset (POR) circuit in the SIM clears the SIM counter 4096 x BUSCLKX4 cycles after power up. 6.3.5 Internal Reset An internal reset clears the SIM counter and the COP counter.
Data Sheet 56 Computer Operating Properly (COP)
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Computer Operating Properly (COP) COP Control Register
6.3.6 COPD (COP Disable) The COPD signal reflects the state of the COP disable bit (COPD) in the configuration register (CONFIG). See Section 5. Configuration Register (CONFIG). 6.3.7 COPRS (COP Rate Select) The COPRS signal reflects the state of the COP rate select bit (COPRS) in the configuration register 1 (CONFIG1). See Section 5. Configuration Register (CONFIG).
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6.4 COP Control Register
The COP control register (COPCTL) is located at address $FFFF and overlaps the reset vector. Writing any value to $FFFF clears the COP counter and starts a new timeout period. Reading location $FFFF returns the low byte of the reset vector.
Address: $FFFF Bit 7 Read: Write: Reset: 6 5 4 3 2 1 Bit 0 LOW BYTE OF RESET VECTOR CLEAR COP COUNTER Unaffected by reset
Figure 6-2. COP Control Register (COPCTL)
6.5 Interrupts
The COP does not generate CPU interrupt requests.
6.6 Monitor Mode
The COP is disabled in monitor mode when VTST is present on the IRQ pin.
6.7 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 6.7.1 Wait Mode The COP continues to operate during wait mode. To prevent a COP reset during wait mode, periodically clear the COP counter.
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Computer Operating Properly (COP)
Data Sheet 57
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Freescale Semiconductor, Inc.
Computer Operating Properly (COP)
6.7.2 Stop Mode Stop mode turns off the BUSCLKX4 input to the COP and clears the SIM counter. Service the COP immediately before entering or after exiting stop mode to ensure a full COP timeout period after entering or exiting stop mode.
6.8 COP Module During Break Mode
The COP is disabled during a break interrupt with monitor mode when BDCOP bit is set in break auxiliary register (BRKAR).
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Data Sheet 58 Computer Operating Properly (COP)
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Data Sheet -- MC68HC908QF4
Section 7. Central Processor Unit (CPU)
7.1 Introduction
The M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of the M68HC05 CPU. The CPU08 Reference Manual (Motorola document order number CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture.
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7.2 Features
Features of the CPU include: * * * * * * * * * * * Object code fully upward-compatible with M68HC05 Family 16-bit stack pointer with stack manipulation instructions 16-bit index register with x-register manipulation instructions 8-MHz CPU internal bus frequency 64-Kbyte program/data memory space 16 addressing modes Memory-to-memory data moves without using accumulator Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions Enhanced binary-coded decimal (BCD) data handling Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes Low-power stop and wait modes
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Central Processor Unit (CPU)
Data Sheet 59
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Central Processor Unit (CPU)
7.3 CPU Registers
Figure 7-1 shows the five CPU registers. CPU registers are not part of the memory map.
7 15 H 15 15 X 0 STACK POINTER (SP) 0 PROGRAM COUNTER (PC) 7 0 V11HINZC CONDITION CODE REGISTER (CCR) 0 ACCUMULATOR (A) 0 INDEX REGISTER (H:X)
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CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO'S COMPLEMENT OVERFLOW FLAG
Figure 7-1. CPU Registers 7.3.1 Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations.
Bit 7 Read: Write: Reset: Unaffected by reset 6 5 4 3 2 1 Bit 0
Figure 7-2. Accumulator (A)
Data Sheet 60 Central Processor Unit (CPU)
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Central Processor Unit (CPU) CPU Registers
7.3.2 Index Register The 16-bit index register allows indexed addressing of a 64-Kbyte memory space. H is the upper byte of the index register, and X is the lower byte. H:X is the concatenated 16-bit index register. In the indexed addressing modes, the CPU uses the contents of the index register to determine the conditional address of the operand. The index register can serve also as a temporary data storage location.
Bit 15 Read: Write: Reset: 0 0 0 0 0 0 0 0 X X X X X X X X Bit 0
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14
13
12
11
10
9
8
7
6
5
4
3
2
1
X = Indeterminate
Figure 7-3. Index Register (H:X) 7.3.3 Stack Pointer The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. In the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an index register to access data on the stack. The CPU uses the contents of the stack pointer to determine the conditional address of the operand.
Bit 15 Read: Write: Reset: 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit 0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Figure 7-4. Stack Pointer (SP) NOTE: The location of the stack is arbitrary and may be relocated anywhere in random-access memory (RAM). Moving the SP out of page 0 ($0000 to $00FF) frees direct address (page 0) space. For correct operation, the stack pointer must point only to RAM locations.
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Central Processor Unit (CPU)
Data Sheet 61
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Central Processor Unit (CPU)
7.3.4 Program Counter The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. Normally, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state.
Bit 15 Read: Write: Reset: Loaded with vector from $FFFE and $FFFF Bit 0
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14
13
12
11
10
9
8
7
6
5
4
3
2
1
Figure 7-5. Program Counter (PC) 7.3.5 Condition Code Register The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the functions of the condition code register.
Bit 7 Read: V Write: Reset: X X = Indeterminate 1 1 X 1 X X X 1 1 H I N Z C 6 5 4 3 2 1 Bit 0
Figure 7-6. Condition Code Register (CCR) V -- Overflow Flag The CPU sets the overflow flag when a two's complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag. 1 = Overflow 0 = No overflow
Data Sheet 62 Central Processor Unit (CPU)
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Central Processor Unit (CPU) CPU Registers
H -- Half-Carry Flag The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C flags to determine the appropriate correction factor. 1 = Carry between bits 3 and 4 0 = No carry between bits 3 and 4 I -- Interrupt Mask When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched. 1 = Interrupts disabled 0 = Interrupts enabled NOTE: To maintain M6805 Family compatibility, the upper byte of the index register (H) is not stacked automatically. If the interrupt service routine modifies H, then the user must stack and unstack H using the PSHH and PULH instructions. After the I bit is cleared, the highest-priority interrupt request is serviced first. A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack and restores the interrupt mask from the stack. After any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (CLI). N -- Negative flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = Negative result 0 = Non-negative result Z -- Zero flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = Zero result 0 = Non-zero result C -- Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions -- such as bit test and branch, shift, and rotate -- also clear or set the carry/borrow flag. 1 = Carry out of bit 7 0 = No carry out of bit 7
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MC68HC908QF4 -- Rev. 1.0 MOTOROLA Central Processor Unit (CPU)
Data Sheet 63
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Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
7.4 Arithmetic/Logic Unit (ALU)
The ALU performs the arithmetic and logic operations defined by the instruction set. Refer to the CPU08 Reference Manual (Motorola document order number CPU08RM/AD) for a description of the instructions and addressing modes and more detail about the architecture of the CPU.
7.5 Low-Power Modes
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The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 7.5.1 Wait Mode The WAIT instruction: * Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set. Disables the CPU clock
* 7.5.2 Stop Mode
The STOP instruction: * Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set. Disables the CPU clock
*
After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay.
7.6 CPU During Break Interrupts
If a break module is present on the MCU, the CPU starts a break interrupt by: * * Loading the instruction register with the SWI instruction Loading the program counter with $FFFC:$FFFD or with $FEFC:$FEFD in monitor mode
The break interrupt begins after completion of the CPU instruction in progress. If the break address register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted.
Data Sheet 64 Central Processor Unit (CPU) MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Central Processor Unit (CPU) Instruction Set Summary
7.7 Instruction Set Summary
Table 7-1 provides a summary of the M68HC08 instruction set. Table 7-1. Instruction Set Summary (Sheet 1 of 7)
Address Mode Opcode Source Form
ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADC opr,SP ADC opr,SP ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X ADD opr,SP ADD opr,SP AIS #opr AIX #opr AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X AND opr,SP AND opr,SP ASL opr ASLA ASLX ASL opr,X ASL ,X ASL opr,SP ASR opr ASRA ASRX ASR opr,X ASR opr,X ASR opr,SP BCC rel
Operation
Description
VH I NZC
Add with Carry
A (A) + (M) + (C)
-
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IMM DIR EXT IX2 IX1 IX SP1 SP2 IMM DIR EXT IX2 IX1 IX SP1 SP2
A9 B9 C9 D9 E9 F9 9EE9 9ED9 AB BB CB DB EB FB 9EEB 9EDB A7 AF A4 B4 C4 D4 E4 F4 9EE4 9ED4
ii dd hh ll ee ff ff ff ee ff ii dd hh ll ee ff ff ff ee ff ii ii ii dd hh ll ee ff ff ff ee ff
Add without Carry
A (A) + (M)
-
Add Immediate Value (Signed) to SP Add Immediate Value (Signed) to H:X
SP (SP) + (16 M) H:X (H:X) + (16 M)
- - - - - - IMM - - - - - - IMM IMM DIR EXT IX2 - IX1 IX SP1 SP2 DIR INH INH IX1 IX SP1 DIR INH INH IX1 IX SP1
Logical AND
A (A) & (M)
0--
Arithmetic Shift Left (Same as LSL)
C b7 b0
0
--
38 dd 48 58 68 ff 78 9E68 ff 37 dd 47 57 67 ff 77 9E67 ff 24 11 13 15 17 19 1B 1D 1F 25 27 rr dd dd dd dd dd dd dd dd rr rr
Arithmetic Shift Right
b7 b0
C
--
Branch if Carry Bit Clear
PC (PC) + 2 + rel ? (C) = 0
- - - - - - REL DIR (b0) DIR (b1) DIR (b2) DIR (b3) - - - - - - DIR (b4) DIR (b5) DIR (b6) DIR (b7) - - - - - - REL - - - - - - REL
BCLR n, opr
Clear Bit n in M
Mn 0
BCS rel BEQ rel
Branch if Carry Bit Set (Same as BLO) Branch if Equal
PC (PC) + 2 + rel ? (C) = 1 PC (PC) + 2 + rel ? (Z) = 1
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Central Processor Unit (CPU)
Data Sheet 65
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Cycles
2 3 4 4 3 2 4 5 2 3 4 4 3 2 4 5 2 2 2 3 4 4 3 2 4 5 4 1 1 4 3 5 4 1 1 4 3 5 3 4 4 4 4 4 4 4 4 3 3
Effect on CCR
Operand
Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
Table 7-1. Instruction Set Summary (Sheet 2 of 7)
Address Mode Opcode Source Form
BGE opr BGT opr BHCC rel BHCS rel BHI rel
Operation
Branch if Greater Than or Equal To (Signed Operands) Branch if Greater Than (Signed Operands) Branch if Half Carry Bit Clear Branch if Half Carry Bit Set Branch if Higher Branch if Higher or Same (Same as BCC) Branch if IRQ Pin High Branch if IRQ Pin Low
Description
PC (PC) + 2 + rel ? (N V) = 0
VH I NZC
- - - - - - REL
90 92 28 29 22 24 2F 2E A5 B5 C5 D5 E5 F5 9EE5 9ED5 93 25 23 91 2C 2B 2D 26 2A 20 01 03 05 07 09 0B 0D 0F 21
rr rr rr rr rr rr rr rr ii dd hh ll ee ff ff ff ee ff rr rr rr rr rr rr rr rr rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr rr
PC (PC) + 2 + rel ? (Z) | (N V) = 0 - - - - - - REL PC (PC) + 2 + rel ? (H) = 0 PC (PC) + 2 + rel ? (H) = 1 PC (PC) + 2 + rel ? (C) | (Z) = 0 PC (PC) + 2 + rel ? (C) = 0 PC (PC) + 2 + rel ? IRQ = 1 PC (PC) + 2 + rel ? IRQ = 0 - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL IMM DIR EXT IX2 - IX1 IX SP1 SP2
3 3 3 3 3 2 3 4 4 3 2 4 5 3 3 3 3 3 3 3 3 3 3 5 5 5 5 5 5 5 5 3
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BHS rel BIH rel BIL rel BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BIT opr,SP BIT opr,SP BLE opr BLO rel BLS rel BLT opr BMC rel BMI rel BMS rel BNE rel BPL rel BRA rel
Bit Test
(A) & (M)
0--
Branch if Less Than or Equal To (Signed Operands) Branch if Lower (Same as BCS) Branch if Lower or Same Branch if Less Than (Signed Operands) Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always
PC (PC) + 2 + rel ? (Z) | (N V) = 1 - - - - - - REL PC (PC) + 2 + rel ? (C) = 1 PC (PC) + 2 + rel ? (C) | (Z) = 1 PC (PC) + 2 + rel ? (N V) =1 PC (PC) + 2 + rel ? (I) = 0 PC (PC) + 2 + rel ? (N) = 1 PC (PC) + 2 + rel ? (I) = 1 PC (PC) + 2 + rel ? (Z) = 0 PC (PC) + 2 + rel ? (N) = 0 PC (PC) + 2 + rel - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL - - - - - - REL DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7)
BRCLR n,opr,rel Branch if Bit n in M Clear
PC (PC) + 3 + rel ? (Mn) = 0
-----
BRN rel
Branch Never
PC (PC) + 2
- - - - - - REL
Data Sheet 66 Central Processor Unit (CPU)
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Cycles
3 3 3
Effect on CCR
Operand
Freescale Semiconductor, Inc.
Central Processor Unit (CPU) Instruction Set Summary
Table 7-1. Instruction Set Summary (Sheet 3 of 7)
Address Mode Opcode Source Form Operation Description Cycles
5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 5 4 4 5 4 6 1 2 3 1 1 1 3 2 4 2 3 4 4 3 2 4 5 4 1 1 4 3 5 3 4
Effect on CCR VH I NZC
BRSET n,opr,rel Branch if Bit n in M Set
PC (PC) + 3 + rel ? (Mn) = 1
-----
DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7)
00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E AD 31 41 51 61 71 9E61 98 9A
dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd dd dd dd dd dd dd dd rr dd rr ii rr ii rr ff rr rr ff rr
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BSET n,opr
Set Bit n in M
Mn 1
DIR (b0) DIR (b1) DIR (b2) DIR (b3) - - - - - - DIR (b4) DIR (b5) DIR (b6) DIR (b7) - - - - - - REL DIR IMM IMM ------ IX1+ IX+ SP1 - - - - - 0 INH - - 0 - - - INH DIR INH INH 0 - - 0 1 - INH IX1 IX SP1 IMM DIR EXT IX2 IX1 IX SP1 SP2 DIR INH INH 1 IX1 IX SP1 IMM DIR
BSR rel
Branch to Subroutine
PC (PC) + 2; push (PCL) SP (SP) - 1; push (PCH) SP (SP) - 1 PC (PC) + rel PC (PC) + 3 + rel ? (A) - (M) = $00 PC (PC) + 3 + rel ? (A) - (M) = $00 PC (PC) + 3 + rel ? (X) - (M) = $00 PC (PC) + 3 + rel ? (A) - (M) = $00 PC (PC) + 2 + rel ? (A) - (M) = $00 PC (PC) + 4 + rel ? (A) - (M) = $00 C0 I0 M $00 A $00 X $00 H $00 M $00 M $00 M $00
CBEQ opr,rel CBEQA #opr,rel CBEQX #opr,rel Compare and Branch if Equal CBEQ opr,X+,rel CBEQ X+,rel CBEQ opr,SP,rel CLC CLI CLR opr CLRA CLRX CLRH CLR opr,X CLR ,X CLR opr,SP CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X CMP opr,SP CMP opr,SP COM opr COMA COMX COM opr,X COM ,X COM opr,SP CPHX #opr CPHX opr Clear Carry Bit Clear Interrupt Mask
Clear
3F dd 4F 5F 8C 6F ff 7F 9E6F ff A1 B1 C1 D1 E1 F1 9EE1 9ED1 ii dd hh ll ee ff ff ff ee ff
Compare A with M
(A) - (M)
--
Complement (One's Complement)
M (M) = $FF - (M) A (A) = $FF - (M) X (X) = $FF - (M) M (M) = $FF - (M) M (M) = $FF - (M) M (M) = $FF - (M) (H:X) - (M:M + 1)
0--
33 dd 43 53 63 ff 73 9E63 ff 65 75 ii ii+1 dd
Compare H:X with M
--
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Central Processor Unit (CPU)
Data Sheet 67
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Operand
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Central Processor Unit (CPU)
Table 7-1. Instruction Set Summary (Sheet 4 of 7)
Address Mode Opcode Source Form
CPX #opr CPX opr CPX opr CPX ,X CPX opr,X CPX opr,X CPX opr,SP CPX opr,SP DAA
Operation
Description
VH I NZC
Compare X with M
(X) - (M)
--
IMM DIR EXT IX2 IX1 IX SP1 SP2 INH
A3 B3 C3 D3 E3 F3 9EE3 9ED3 72 3B 4B 5B 6B 7B 9E6B
ii dd hh ll ee ff ff ff ee ff
Decimal Adjust A
(A)10
U--
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DBNZ opr,rel DBNZA rel DBNZX rel Decrement and Branch if Not Zero DBNZ opr,X,rel DBNZ X,rel DBNZ opr,SP,rel DEC opr DECA DECX DEC opr,X DEC ,X DEC opr,SP DIV EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X EOR opr,SP EOR opr,SP INC opr INCA INCX INC opr,X INC ,X INC opr,SP JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDA opr,SP LDA opr,SP
A (A) - 1 or M (M) - 1 or X (X) - 1 PC (PC) + 3 + rel ? (result) 0 DIR PC (PC) + 2 + rel ? (result) 0 INH PC (PC) + 2 + rel ? (result) 0 - - - - - - INH PC (PC) + 3 + rel ? (result) 0 IX1 PC (PC) + 2 + rel ? (result) 0 IX PC (PC) + 4 + rel ? (result) 0 SP1 M (M) - 1 A (A) - 1 X (X) - 1 M (M) - 1 M (M) - 1 M (M) - 1 A (H:A)/(X) H Remainder DIR INH INH - IX1 IX SP1 INH IMM DIR EXT - IX2 IX1 IX SP1 SP2 DIR INH - INH IX1 IX SP1
dd rr rr rr ff rr rr ff rr
Decrement
--
3A dd 4A 5A 6A ff 7A 9E6A ff 52 A8 B8 C8 D8 E8 F8 9EE8 9ED8 ii dd hh ll ee ff ff ff ee ff
Divide
----
Exclusive OR M with A
A (A M)
0--
Increment
M (M) + 1 A (A) + 1 X (X) + 1 M (M) + 1 M (M) + 1 M (M) + 1
--
3C dd 4C 5C 6C ff 7C 9E6C ff BC CC DC EC FC BD CD DD ED FD A6 B6 C6 D6 E6 F6 9EE6 9ED6 dd hh ll ee ff ff dd hh ll ee ff ff ii dd hh ll ee ff ff ff ee ff
Jump
PC Jump Address
DIR EXT - - - - - - IX2 IX1 IX DIR EXT - - - - - - IX2 IX1 IX IMM DIR EXT IX2 - IX1 IX SP1 SP2
Jump to Subroutine
PC (PC) + n (n = 1, 2, or 3) Push (PCL); SP (SP) - 1 Push (PCH); SP (SP) - 1 PC Unconditional Address
Load A from M
A (M)
0--
Data Sheet 68 Central Processor Unit (CPU)
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Cycles
2 3 4 4 3 2 4 5 2 5 3 3 5 4 6 4 1 1 4 3 5 7 2 3 4 4 3 2 4 5 4 1 1 4 3 5 2 3 4 3 2 4 5 6 5 4 2 3 4 4 3 2 4 5
Effect on CCR
Operand
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Central Processor Unit (CPU) Instruction Set Summary
Table 7-1. Instruction Set Summary (Sheet 5 of 7)
Address Mode Opcode Source Form
LDHX #opr LDHX opr LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LDX opr,SP LDX opr,SP LSL opr LSLA LSLX LSL opr,X LSL ,X LSL opr,SP LSR opr LSRA LSRX LSR opr,X LSR ,X LSR opr,SP MOV opr,opr MOV opr,X+ MOV #opr,opr MOV X+,opr MUL NEG opr NEGA NEGX NEG opr,X NEG ,X NEG opr,SP NOP NSA ORA #opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X ORA opr,SP ORA opr,SP PSHA PSHH PSHX PULA PULH PULX
Operation
Description
H:X (M:M + 1)
VH I NZC
Load H:X from M 0--
- IMM DIR IMM DIR EXT IX2 - IX1 IX SP1 SP2 DIR INH INH IX1 IX SP1 DIR INH INH IX1 IX SP1 - DD DIX+ IMD IX+D
45 55 AE BE CE DE EE FE 9EEE 9EDE
ii jj dd ii dd hh ll ee ff ff ff ee ff
Load X from M
X (M)
0--
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Logical Shift Left (Same as ASL)
C b7 b0
0
--
38 dd 48 58 68 ff 78 9E68 ff 34 dd 44 54 64 ff 74 9E64 ff 4E 5E 6E 7E 42 30 dd 40 50 60 ff 70 9E60 ff 9D 62 AA BA CA DA EA FA 9EEA 9EDA 87 8B 89 86 8A 88 ii dd hh ll ee ff ff ff ee ff dd dd dd ii dd dd
Logical Shift Right
0 b7 b0
C
--0
Move Unsigned multiply
(M)Destination (M)Source H:X (H:X) + 1 (IX+D, DIX+) X:A (X) x (A) M -(M) = $00 - (M) A -(A) = $00 - (A) X -(X) = $00 - (X) M -(M) = $00 - (M) M -(M) = $00 - (M) None A (A[3:0]:A[7:4])
0--
- 0 - - - 0 INH DIR INH INH IX1 IX SP1
Negate (Two's Complement)
--
No Operation Nibble Swap A
- - - - - - INH - - - - - - INH IMM DIR EXT - IX2 IX1 IX SP1 SP2
Inclusive OR A and M
A (A) | (M)
0--
Push A onto Stack Push H onto Stack Push X onto Stack Pull A from Stack Pull H from Stack Pull X from Stack
Push (A); SP (SP) - 1 Push (H); SP (SP) - 1 Push (X); SP (SP) - 1 SP (SP + 1); Pull (A) SP (SP + 1); Pull (H) SP (SP + 1); Pull (X)
- - - - - - INH - - - - - - INH - - - - - - INH - - - - - - INH - - - - - - INH - - - - - - INH
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Central Processor Unit (CPU)
Data Sheet 69
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Cycles
3 4 2 3 4 4 3 2 4 5 4 1 1 4 3 5 4 1 1 4 3 5 5 4 4 4 5 4 1 1 4 3 5 1 3 2 3 4 4 3 2 4 5 2 2 2 2 2 2
Effect on CCR
Operand
Freescale Semiconductor, Inc.
Central Processor Unit (CPU)
Table 7-1. Instruction Set Summary (Sheet 6 of 7)
Address Mode Opcode Source Form
ROL opr ROLA ROLX ROL opr,X ROL ,X ROL opr,SP ROR opr RORA RORX ROR opr,X ROR ,X ROR opr,SP RSP
Operation
Description
VH I NZC
Rotate Left through Carry
C b7 b0
--
DIR INH INH IX1 IX SP1 DIR INH INH IX1 IX SP1
39 dd 49 59 69 ff 79 9E69 ff 36 dd 46 56 66 ff 76 9E66 ff 9C
Rotate Right through Carry
b7 b0
C
--
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Reset Stack Pointer
SP $FF SP (SP) + 1; Pull (CCR) SP (SP) + 1; Pull (A) SP (SP) + 1; Pull (X) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL) SP SP + 1; Pull (PCH) SP SP + 1; Pull (PCL)
- - - - - - INH
RTI
Return from Interrupt
INH
80
RTS SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X SBC opr,SP SBC opr,SP SEC SEI STA opr STA opr STA opr,X STA opr,X STA ,X STA opr,SP STA opr,SP STHX opr STOP STX opr STX opr STX opr,X STX opr,X STX ,X STX opr,SP STX opr,SP SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X SUB opr,SP SUB opr,SP
Return from Subroutine
- - - - - - INH IMM DIR EXT IX2 IX1 IX SP1 SP2
81 A2 B2 C2 D2 E2 F2 9EE2 9ED2 99 9B B7 C7 D7 E7 F7 9EE7 9ED7 35 8E BF CF DF EF FF 9EEF 9EDF A0 B0 C0 D0 E0 F0 9EE0 9ED0 dd hh ll ee ff ff ff ee ff ii dd hh ll ee ff ff ff ee ff dd hh ll ee ff ff ff ee ff dd ii dd hh ll ee ff ff ff ee ff
Subtract with Carry
A (A) - (M) - (C)
--
Set Carry Bit Set Interrupt Mask
C1 I1
- - - - - 1 INH - - 1 - - - INH DIR EXT IX2 - IX1 IX SP1 SP2 - DIR
Store A in M
M (A)
0--
Store H:X in M Enable Interrupts, Stop Processing, Refer to MCU Documentation
(M:M + 1) (H:X) I 0; Stop Processing
0--
- - 0 - - - INH DIR EXT IX2 - IX1 IX SP1 SP2 IMM DIR EXT IX2 IX1 IX SP1 SP2
Store X in M
M (X)
0--
Subtract
A (A) - (M)
--
Data Sheet 70 Central Processor Unit (CPU)
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Cycles
4 1 1 4 3 5 4 1 1 4 3 5 1 7 4 2 3 4 4 3 2 4 5 1 2 3 4 4 3 2 4 5 4 1 3 4 4 3 2 4 5 2 3 4 4 3 2 4 5
Effect on CCR
Operand
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Central Processor Unit (CPU) Opcode Map
Table 7-1. Instruction Set Summary (Sheet 7 of 7)
Address Mode Opcode Source Form Operation Description
PC (PC) + 1; Push (PCL) SP (SP) - 1; Push (PCH) SP (SP) - 1; Push (X) SP (SP) - 1; Push (A) SP (SP) - 1; Push (CCR) SP (SP) - 1; I 1 PCH Interrupt Vector High Byte PCL Interrupt Vector Low Byte CCR (A) X (A) A (CCR)
VH I NZC
SWI
Software Interrupt
- - 1 - - - INH
83
TAP
Transfer A to CCR Transfer A to X Transfer CCR to A
INH - - - - - - INH - - - - - - INH DIR INH - INH IX1 IX SP1
84 97 85 3D dd 4D 5D 6D ff 7D 9E6D ff 95 9F 94 8F
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TAX TPA TST opr TSTA TSTX TST opr,X TST ,X TST opr,SP TSX TXA TXS WAIT A C CCR dd dd rr DD DIR DIX+ ee ff EXT ff H H hh ll I ii IMD IMM INH IX IX+ IX+D IX1 IX1+ IX2 M N
Test for Negative or Zero
(A) - $00 or (X) - $00 or (M) - $00
0--
Transfer SP to H:X Transfer X to A Transfer H:X to SP Enable Interrupts; Wait for Interrupt
H:X (SP) + 1 A (X) (SP) (H:X) - 1 I bit 0; Inhibit CPU clocking until interrupted n opr PC PCH PCL REL rel rr SP1 SP2 SP U V X Z & |
- - - - - - INH - - - - - - INH - - - - - - INH - - 0 - - - INH
Accumulator Carry/borrow bit Condition code register Direct address of operand Direct address of operand and relative offset of branch instruction Direct to direct addressing mode Direct addressing mode Direct to indexed with post increment addressing mode High and low bytes of offset in indexed, 16-bit offset addressing Extended addressing mode Offset byte in indexed, 8-bit offset addressing Half-carry bit Index register high byte High and low bytes of operand address in extended addressing Interrupt mask Immediate operand byte Immediate source to direct destination addressing mode Immediate addressing mode Inherent addressing mode Indexed, no offset addressing mode Indexed, no offset, post increment addressing mode Indexed with post increment to direct addressing mode Indexed, 8-bit offset addressing mode Indexed, 8-bit offset, post increment addressing mode Indexed, 16-bit offset addressing mode Memory location Negative bit
() -( ) # ? : --
Any bit Operand (one or two bytes) Program counter Program counter high byte Program counter low byte Relative addressing mode Relative program counter offset byte Relative program counter offset byte Stack pointer, 8-bit offset addressing mode Stack pointer 16-bit offset addressing mode Stack pointer Undefined Overflow bit Index register low byte Zero bit Logical AND Logical OR Logical EXCLUSIVE OR Contents of Negation (two's complement) Immediate value Sign extend Loaded with If Concatenated with Set or cleared Not affected
7.8 Opcode Map
See Table 7-2.
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Central Processor Unit (CPU) Data Sheet 71
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Cycles
9 2 1 1 3 1 1 3 2 4 2 1 2 1
Effect on CCR
Operand
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Table 7-2. Opcode Map
DIR 3 4 5 6 9E6 7 8 9 A B C D 9ED E 9EE F INH Read-Modify-Write INH IX1 SP1 IX IMM DIR EXT IX1 SP1 IX Control INH INH Register/Memory IX2 SP2 2
Central Processor Unit (CPU)
72
2 SUB 2 IMM 2 CMP 2 IMM 2 SBC 2 IMM 2 CPX 2 IMM 2 AND 2 IMM 2 BIT 2 IMM 2 LDA 2 IMM 2 AIS 2 IMM 2 EOR 2 IMM 2 ADC 2 IMM 2 ORA 2 IMM 2 ADD 2 IMM 5 SUB 4 SP2 5 CMP 4 SP2 5 SBC 4 SP2 5 CPX 4 SP2 5 AND 4 SP2 5 BIT 4 SP2 5 LDA 4 SP2 5 STA 4 SP2 5 EOR 4 SP2 5 ADC 4 SP2 5 ORA 4 SP2 5 ADD 4 SP2 4 SUB 3 SP1 4 CMP 3 SP1 4 SBC 3 SP1 4 CPX 3 SP1 4 AND 3 SP1 4 BIT 3 SP1 4 LDA 3 SP1 4 STA 3 SP1 4 EOR 3 SP1 4 ADC 3 SP1 4 ORA 3 SP1 4 ADD 3 SP1 4 1 NEG NEGA 2 DIR 1 INH 5 4 CBEQ CBEQA 3 DIR 3 IMM 5 MUL 1 INH 4 1 COM COMA 2 DIR 1 INH 4 1 LSR LSRA 2 DIR 1 INH 4 3 STHX LDHX 2 DIR 3 IMM 4 1 ROR RORA 2 DIR 1 INH 4 1 ASR ASRA 2 DIR 1 INH 4 1 LSL LSLA 2 DIR 1 INH 4 1 ROL ROLA 2 DIR 1 INH 4 1 DEC DECA 2 DIR 1 INH 5 3 DBNZ DBNZA 3 DIR 2 INH 4 1 INC INCA 2 DIR 1 INH 3 1 TST TSTA 2 DIR 1 INH 5 MOV 3 DD 3 1 CLR CLRA 2 DIR 1 INH
MSB LSB
Data Sheet
Bit Manipulation DIR DIR
Branch REL
MSB
0
1
LSB
0
1
2
3
4
5
6
7
8
9
Central Processor Unit (CPU)
0 Low Byte of Opcode in Hexadecimal 0 SP1 Stack Pointer, 8-Bit Offset SP2 Stack Pointer, 16-Bit Offset IX+ Indexed, No Offset with Post Increment IX1+ Indexed, 1-Byte Offset with Post Increment
A
B
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C
D
E
F
5 BRSET0 3 DIR 5 BRCLR0 3 DIR 5 BRSET1 3 DIR 5 BRCLR1 3 DIR 5 BRSET2 3 DIR 5 BRCLR2 3 DIR 5 BRSET3 3 DIR 5 BRCLR3 3 DIR 5 BRSET4 3 DIR 5 BRCLR4 3 DIR 5 BRSET5 3 DIR 5 BRCLR5 3 DIR 5 BRSET6 3 DIR 5 BRCLR6 3 DIR 5 BRSET7 3 DIR 5 BRCLR7 3 DIR
4 BSET0 2 DIR 4 BCLR0 2 DIR 4 BSET1 2 DIR 4 BCLR1 2 DIR 4 BSET2 2 DIR 4 BCLR2 2 DIR 4 BSET3 2 DIR 4 BCLR3 2 DIR 4 BSET4 2 DIR 4 BCLR4 2 DIR 4 BSET5 2 DIR 4 BCLR5 2 DIR 4 BSET6 2 DIR 4 BCLR6 2 DIR 4 BSET7 2 DIR 4 BCLR7 2 DIR
3 BRA 2 REL 3 BRN 2 REL 3 BHI 2 REL 3 BLS 2 REL 3 BCC 2 REL 3 BCS 2 REL 3 BNE 2 REL 3 BEQ 2 REL 3 BHCC 2 REL 3 BHCS 2 REL 3 BPL 2 REL 3 BMI 2 REL 3 BMC 2 REL 3 BMS 2 REL 3 BIL 2 REL 3 BIH 2 REL
1 NEGX 1 INH 4 CBEQX 3 IMM 7 DIV 1 INH 1 COMX 1 INH 1 LSRX 1 INH 4 LDHX 2 DIR 1 RORX 1 INH 1 ASRX 1 INH 1 LSLX 1 INH 1 ROLX 1 INH 1 DECX 1 INH 3 DBNZX 2 INH 1 INCX 1 INH 1 TSTX 1 INH 4 MOV 2 DIX+ 1 CLRX 1 INH
4 NEG 2 IX1 5 CBEQ 3 IX1+ 3 NSA 1 INH 4 COM 2 IX1 4 LSR 2 IX1 3 CPHX 3 IMM 4 ROR 2 IX1 4 ASR 2 IX1 4 LSL 2 IX1 4 ROL 2 IX1 4 DEC 2 IX1 5 DBNZ 3 IX1 4 INC 2 IX1 3 TST 2 IX1 4 MOV 3 IMD 3 CLR 2 IX1
5 3 NEG NEG 3 SP1 1 IX 6 4 CBEQ CBEQ 4 SP1 2 IX+ 2 DAA 1 INH 5 3 COM COM 3 SP1 1 IX 5 3 LSR LSR 3 SP1 1 IX 4 CPHX 2 DIR 5 3 ROR ROR 3 SP1 1 IX 5 3 ASR ASR 3 SP1 1 IX 5 3 LSL LSL 3 SP1 1 IX 5 3 ROL ROL 3 SP1 1 IX 5 3 DEC DEC 3 SP1 1 IX 6 4 DBNZ DBNZ 4 SP1 2 IX 5 3 INC INC 3 SP1 1 IX 4 2 TST TST 3 SP1 1 IX 4 MOV 2 IX+D 4 2 CLR CLR 3 SP1 1 IX
7 3 RTI BGE 1 INH 2 REL 4 3 RTS BLT 1 INH 2 REL 3 BGT 2 REL 9 3 SWI BLE 1 INH 2 REL 2 2 TAP TXS 1 INH 1 INH 1 2 TPA TSX 1 INH 1 INH 2 PULA 1 INH 2 1 PSHA TAX 1 INH 1 INH 2 1 PULX CLC 1 INH 1 INH 2 1 PSHX SEC 1 INH 1 INH 2 2 PULH CLI 1 INH 1 INH 2 2 PSHH SEI 1 INH 1 INH 1 1 CLRH RSP 1 INH 1 INH 1 NOP 1 INH 1 STOP * 1 INH 1 1 WAIT TXA 1 INH 1 INH
3 SUB 2 DIR 3 CMP 2 DIR 3 SBC 2 DIR 3 CPX 2 DIR 3 AND 2 DIR 3 BIT 2 DIR 3 LDA 2 DIR 3 STA 2 DIR 3 EOR 2 DIR 3 ADC 2 DIR 3 ORA 2 DIR 3 ADD 2 DIR 2 JMP 2 DIR 4 4 BSR JSR 2 REL 2 DIR 2 3 LDX LDX 2 IMM 2 DIR 2 3 AIX STX 2 IMM 2 DIR
4 SUB 3 EXT 4 CMP 3 EXT 4 SBC 3 EXT 4 CPX 3 EXT 4 AND 3 EXT 4 BIT 3 EXT 4 LDA 3 EXT 4 STA 3 EXT 4 EOR 3 EXT 4 ADC 3 EXT 4 ORA 3 EXT 4 ADD 3 EXT 3 JMP 3 EXT 5 JSR 3 EXT 4 LDX 3 EXT 4 STX 3 EXT
4 SUB 3 IX2 4 CMP 3 IX2 4 SBC 3 IX2 4 CPX 3 IX2 4 AND 3 IX2 4 BIT 3 IX2 4 LDA 3 IX2 4 STA 3 IX2 4 EOR 3 IX2 4 ADC 3 IX2 4 ORA 3 IX2 4 ADD 3 IX2 4 JMP 3 IX2 6 JSR 3 IX2 4 LDX 3 IX2 4 STX 3 IX2
3 SUB 2 IX1 3 CMP 2 IX1 3 SBC 2 IX1 3 CPX 2 IX1 3 AND 2 IX1 3 BIT 2 IX1 3 LDA 2 IX1 3 STA 2 IX1 3 EOR 2 IX1 3 ADC 2 IX1 3 ORA 2 IX1 3 ADD 2 IX1 3 JMP 2 IX1 5 JSR 2 IX1 5 3 LDX LDX 4 SP2 2 IX1 5 3 STX STX 4 SP2 2 IX1
2 SUB 1 IX 2 CMP 1 IX 2 SBC 1 IX 2 CPX 1 IX 2 AND 1 IX 2 BIT 1 IX 2 LDA 1 IX 2 STA 1 IX 2 EOR 1 IX 2 ADC 1 IX 2 ORA 1 IX 2 ADD 1 IX 2 JMP 1 IX 4 JSR 1 IX 4 2 LDX LDX 3 SP1 1 IX 4 2 STX STX 3 SP1 1 IX
MC68HC908QF4 -- Rev. 1.0
Inherent REL Relative Immediate IX Indexed, No Offset Direct IX1 Indexed, 8-Bit Offset Extended IX2 Indexed, 16-Bit Offset Direct-Direct IMD Immediate-Direct Indexed-Direct DIX+ Direct-Indexed *Pre-byte for stack pointer indexed instructions
INH IMM DIR EXT DD IX+D
High Byte of Opcode in Hexadecimal 5 Cycles BRSET0 Opcode Mnemonic 3 DIR Number of Bytes / Addressing Mode
MOTOROLA
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Data Sheet -- MC68HC908QF4
Section 8. External Interrupt (IRQ)
8.1 Introduction
The IRQ pin (external interrupt), shared with PTA2 (general purpose input) and keyboard interrupt (KBI), provides a maskable interrupt input.
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8.2 Features
Features of the IRQ module include the following: * External interrupt pin, IRQ * IRQ interrupt control bits * Hysteresis buffer * Programmable edge-only or edge and level interrupt sensitivity * Automatic interrupt acknowledge * Selectable internal pullup resistor
8.3 Functional Description
IRQ pin functionality is enabled by setting configuration register 2 (CONFIG2) IRQEN bit accordingly. A zero disables the IRQ function and IRQ will assume the other shared functionalities. A one enables the IRQ function. A falling edge on the external interrupt pin can latch a central processor unit (CPU) interrupt request. Figure 8-2 shows the structure of the IRQ module. Interrupt signals on the IRQ pin are latched into the IRQ latch. An interrupt latch remains set until one of the following actions occurs: * Vector fetch -- A vector fetch automatically generates an interrupt acknowledge signal that clears the IRQ latch. * Software clear -- Software can clear the interrupt latch by writing to the acknowledge bit in the interrupt status and control register (INTSCR). Writing a 1 to the ACK bit clears the IRQ latch. * Reset -- A reset automatically clears the interrupt latch. The external interrupt pin is falling-edge-triggered out of reset and is software-configurable to be either falling-edge or falling-edge and low-level triggered. The MODE bit in the INTSCR controls the triggering sensitivity of the IRQ pin. When the interrupt pin is edge-triggered only (MODE = 0), the CPU interrupt request remains set until a vector fetch, software clear, or reset occurs.
MC68HC908QF4 -- Rev. 1.0 MOTOROLA External Interrupt (IRQ)
Data Sheet 73
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External Interrupt (IRQ)
PTA0/AD0/TCH0/KBI0 PTA1/AD1/TCH1/KBI1 DDRA PTA PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 M68HC08 CPU PTB0 PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 CLOCK GENERATOR (OSCILLATOR)
SYSTEM INTEGRATION MODULE SINGLE INTERRUPT MODULE BREAK MODULE POWER-ON RESET MODULE KEYBOARD INTERRUPT MODULE 16-BIT TIMER MODULE COP MODULE VCC MODE PLLEN DATA BS OP1 GND REXT XTAL1 XTAL0 UPCLK PFD
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8-BIT ADC
DDRB
PTB
MC68HC908QF4 4096 BYTES USER FLASH
128 BYTES RAM
MONITOR ROM
UHF TRANSMITTER
VDD POWER SUPPLY VSS
RST, IRQ: Pins have internal (about 30K Ohms) pull up PTA[0:5]: High current sink and source capability PTA[0:5]: Pins have programmable keyboard interrupt and pull up
Figure 8-1. Block Diagram Highlighting IRQ Block and Pins
Data Sheet 74 External Interrupt (IRQ)
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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External Interrupt (IRQ) Functional Description
ACK RESET INTERNAL ADDRESS BUS VECTOR FETCH DECODER VDD IRQPUD INTERNAL PULLUP DEVICE VDD D IRQ CLR Q SYNCHRONIZER IRQF TO CPU FOR BIL/BIH INSTRUCTIONS
CK IRQ FF IMASK
IRQ INTERRUPT REQUEST
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MODE HIGH VOLTAGE DETECT TO MODE SELECT LOGIC
Figure 8-2. IRQ Module Block Diagram When the interrupt pin is both falling-edge and low-level triggered (MODE = 1), the CPU interrupt request remains set until both of the following occur: * * Vector fetch or software clear Return of the interrupt pin to logic 1
The vector fetch or software clear may occur before or after the interrupt pin returns to logic 1. As long as the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE control bit, thereby clearing the interrupt even if the pin stays low. When set, the IMASK bit in the INTSCR mask all external interrupt requests. A latched interrupt request is not presented to the interrupt priority logic unless the IMASK bit is clear. NOTE: The interrupt mask (I) in the condition code register (CCR) masks all interrupt requests, including external interrupt requests. See 14.6 Exception Control. Figure 8-3 provides a summary of the IRQ I/O register.
Addr. $001D Register Name IRQ Status and Control Read: Register (INTSCR) Write: See page 77. Reset: Bit 7 0 0 6 0 0 = Unimplemented 5 0 0 4 0 0 3 IRQF 0 2 0 ACK 0 1 IMASK 0 Bit 0 MODE 0
Figure 8-3. IRQ I/O Register Summary
MC68HC908QF4 -- Rev. 1.0 MOTOROLA External Interrupt (IRQ) Data Sheet 75
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External Interrupt (IRQ)
8.4 IRQ Pin
A falling edge on the IRQ pin can latch an interrupt request into the IRQ latch. A vector fetch, software clear, or reset clears the IRQ latch. If the MODE bit is set, the IRQ pin is both falling-edge sensitive and low-level sensitive. With MODE set, both of the following actions must occur to clear IRQ: * Vector fetch or software clear -- A vector fetch generates an interrupt acknowledge signal to clear the latch. Software may generate the interrupt acknowledge signal by writing a 1 to the ACK bit in the interrupt status and control register (INTSCR). The ACK bit is useful in applications that poll the IRQ pin and require software to clear the IRQ latch. Writing to the ACK bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. Setting ACK does not affect subsequent transitions on the IRQ pin. A falling edge that occurs after writing to the ACK bit latches another interrupt request. If the IRQ mask bit, IMASK, is clear, the CPU loads the program counter with the vector address at locations $FFFA and $FFFB. * Return of the IRQ pin to logic 1 -- As long as the IRQ pin is at logic 0, IRQ remains active. The vector fetch or software clear and the return of the IRQ pin to logic 1 may occur in any order. The interrupt request remains pending as long as the IRQ pin is at logic 0. A reset will clear the latch and the MODE control bit, thereby clearing the interrupt even if the pin stays low. If the MODE bit is clear, the IRQ pin is falling-edge sensitive only. With MODE clear, a vector fetch or software clear immediately clears the IRQ latch. The IRQF bit in the INTSCR register can be used to check for pending interrupts. The IRQF bit is not affected by the IMASK bit, which makes it useful in applications where polling is preferred. NOTE: When the IRQ function is enabled in the CONFIG2 register, the BIH and BIL instructions can be used to read the logic level on the IRQ pin. If the IRQ function is disabled, these instructions will behave as if the IRQ pin is a logic 1, regardless of the actual level on the pin. Conversely, when the IRQ function is enabled, bit 2 of the port A data register will always read a 0. When using the level-sensitive interrupt trigger, avoid false interrupts by masking interrupt requests in the interrupt routine. An internal pullup resistor to VDD is connected to the IRQ pin; this can be disabled by setting the IRQPUD bit in the CONFIG2 register ($001E).
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NOTE:
8.5 IRQ Module During Break Interrupts
The system integration module (SIM) controls whether the IRQ latch can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear the latches during the break state. See Section 14. System Integration Module (SIM).
Data Sheet 76 External Interrupt (IRQ) MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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External Interrupt (IRQ) IRQ Status and Control Register
To allow software to clear the IRQ latch during a break interrupt, write a 1 to the BCFE bit. If a latch is cleared during the break state, it remains cleared when the MCU exits the break state. To protect the latches during the break state, write a 0 to the BCFE bit. With BCFE at 0 (its default state), writing to the ACK bit in the IRQ status and control register during the break state has no effect on the IRQ latch.
8.6 IRQ Status and Control Register
The IRQ status and control register (ISCR) controls and monitors operation of the IRQ module, see Section 5. Configuration Register (CONFIG).
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The ISCR has the following functions: * Shows the state of the IRQ flag * Clears the IRQ latch * Masks IRQ and interrupt request * Controls triggering sensitivity of the IRQ interrupt pin
Address: $001D Bit 7 Read: Write: Reset: 0 0 0 0 0 = Unimplemented 0 6 0 5 0 4 0 3 IRQF ACK 0 2 1 IMASK 0 Bit 0 MODE 0
Figure 8-4. IRQ Status and Control Register (INTSCR) IRQF -- IRQ Flag This read-only status bit is high when the IRQ interrupt is pending. 1 = IRQ interrupt pending 0 = IRQ interrupt not pending ACK -- IRQ Interrupt Request Acknowledge Bit Writing a 1 to this write-only bit clears the IRQ latch. ACK always reads as 0. Reset clears ACK. IMASK -- IRQ Interrupt Mask Bit Writing a 1 to this read/write bit disables IRQ interrupt requests. Reset clears IMASK. 1 = IRQ interrupt requests disabled 0 = IRQ interrupt requests enabled MODE -- IRQ Edge/Level Select Bit This read/write bit controls the triggering sensitivity of the IRQ pin. Reset clears MODE. 1 = IRQ interrupt requests on falling edges and low levels 0 = IRQ interrupt requests on falling edges only
MC68HC908QF4 -- Rev. 1.0 MOTOROLA External Interrupt (IRQ)
Data Sheet 77
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External Interrupt (IRQ)
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Data Sheet 78 External Interrupt (IRQ)
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Data Sheet -- MC68HC908QF4
Section 9. Keyboard Interrupt Module (KBI)
9.1 Introduction
The keyboard interrupt module (KBI) provides six independently maskable external interrupts, which are accessible via the PTA0-PTA5 pins.
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9.2 Features
Features of the keyboard interrupt module include: * * * * Six keyboard interrupt pins with separate keyboard interrupt enable bits and one keyboard interrupt mask Software configurable pullup device if input pin is configured as input port bit Programmable edge-only or edge and level interrupt sensitivity Exit from low-power modes
Figure 9-1 provides a summary of the input/output (I/O) registers
Addr.
Register Name
Bit 7 0
6 0
5 0
4 0
3 KEYF
2 0
1 IMASKK
Bit 0 MODEK 0 KBIE0 0
Read: Keyboard Status and Control $001A Register (KBSCR) Write: See page 84. Reset: Read: Keyboard Interrupt Enable Register (KBIER) Write: See page 85. Reset:
ACKK 0 0 AWUIE 0 0 = Unimplemented KBIE5 0 KBIE4 0 KBIE3 0 KBIE2 0 KBIE1 0 0 0 0 0 0 0
$001B
Figure 9-1. KBI I/O Register Summary
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Keyboard Interrupt Module (KBI)
Data Sheet 79
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Keyboard Interrupt Module (KBI)
PTA0/AD0/TCH0/KBI0 PTA1/AD1/TCH1/KBI1 DDRA PTA PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 M68HC08 CPU PTB0 PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 SINGLE INTERRUPT MODULE DDRB BREAK MODULE POWER-ON RESET MODULE KEYBOARD INTERRUPT MODULE 16-BIT TIMER MODULE COP MODULE VCC MODE PLLEN DATA BS OP1 GND REXT XTAL1 XTAL0 UPCLK PFD CLOCK GENERATOR (OSCILLATOR)
SYSTEM INTEGRATION MODULE
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8-BIT ADC
PTB
MC68HC908QF4 4096 BYTES USER FLASH
128 BYTES RAM
MONITOR ROM
UHF TRANSMITTER
VDD POWER SUPPLY VSS
RST, IRQ: Pins have internal (about 30K Ohms) pull up PTA[0:5]: High current sink and source capability PTA[0:5]: Pins have programmable keyboard interrupt and pull up
Figure 9-2. Block Diagram Highlighting KBI Block and Pins
Data Sheet 80 Keyboard Interrupt Module (KBI)
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Keyboard Interrupt Module (KBI) Functional Description
INTERNAL BUS
VECTOR FETCH DECODER KBI0 VDD ACKK RESET D CLR Q SYNCHRONIZER CK KEYBOARD INTERRUPT REQUEST KEYF
KBIE0 TO PULLUP ENABLE
. . .
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KBI5
KEYBOARD INTERRUPT FF MODEK KBIE5
IMASKK
TO PULLUP ENABLE
AWUIREQ(1)
1. For AWUGEN logic refer to Figure 4-2. Auto Wakeup Interrupt Request Generation Logic.
Figure 9-3. Keyboard Interrupt Block Diagram
9.3 Functional Description
The keyboard interrupt module controls the enabling/disabling of interrupt functions on the six port A pins. These six pins can be enabled/disabled independently of each other. 9.3.1 Keyboard Operation Writing to the KBIE0-KBIE5 bits in the keyboard interrupt enable register (KBIER) independently enables or disables each port A pin as a keyboard interrupt pin. Enabling a keyboard interrupt pin in port A also enables its internal pullup device irrespective of PTAPUEx bits in the port A input pullup enable register (see 13.2.3 Port A Input Pullup Enable Register). A logic 0 applied to an enabled keyboard interrupt pin latches a keyboard interrupt request. A keyboard interrupt is latched when one or more keyboard interrupt inputs goes low after all were high. The MODEK bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt. * If the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard interrupt input does not latch an interrupt request if another keyboard pin is already low. To prevent losing an interrupt request on one input because another input is still low, software can disable the latter input while it is low. If the keyboard interrupt is falling edge and low-level sensitive, an interrupt request is present as long as any keyboard interrupt input is low.
Data Sheet Keyboard Interrupt Module (KBI) 81
*
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Keyboard Interrupt Module (KBI)
If the MODEK bit is set, the keyboard interrupt inputs are both falling edge and low-level sensitive, and both of the following actions must occur to clear a keyboard interrupt request: * Vector fetch or software clear -- A vector fetch generates an interrupt acknowledge signal to clear the interrupt request. Software may generate the interrupt acknowledge signal by writing a 1 to the ACKK bit in the keyboard status and control register (KBSCR). The ACKK bit is useful in applications that poll the keyboard interrupt inputs and require software to clear the keyboard interrupt request. Writing to the ACKK bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. Setting ACKK does not affect subsequent transitions on the keyboard interrupt inputs. A falling edge that occurs after writing to the ACKK bit latches another interrupt request. If the keyboard interrupt mask bit, IMASKK, is clear, the central processor unit (CPU) loads the program counter with the vector address at locations $FFE0 and $FFE1. Return of all enabled keyboard interrupt inputs to logic 1 -- As long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set. The auto wakeup interrupt input, AWUIREQ, will be cleared only by writing to ACKK bit in KBSCR or reset.
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*
The vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order. If the MODEK bit is clear, the keyboard interrupt pin is falling-edge sensitive only. With MODEK clear, a vector fetch or software clear immediately clears the keyboard interrupt request. Reset clears the keyboard interrupt request and the MODEK bit, clearing the interrupt request even if a keyboard interrupt input stays at logic 0. The keyboard flag bit (KEYF) in the keyboard status and control register can be used to see if a pending interrupt exists. The KEYF bit is not affected by the keyboard interrupt mask bit (IMASKK) which makes it useful in applications where polling is preferred. To determine the logic level on a keyboard interrupt pin, use the data direction register to configure the pin as an input and then read the data register. NOTE: Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. However, the data direction register bit must be a 0 for software to read the pin.
Data Sheet 82 Keyboard Interrupt Module (KBI)
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Keyboard Interrupt Module (KBI) Wait Mode
9.3.2 Keyboard Initialization When a keyboard interrupt pin is enabled, it takes time for the internal pullup to reach a logic 1. Therefore a false interrupt can occur as soon as the pin is enabled. To prevent a false interrupt on keyboard initialization: 1. Mask keyboard interrupts by setting the IMASKK bit in the keyboard status and control register. 2. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register. 3. Write to the ACKK bit in the keyboard status and control register to clear any false interrupts. 4. Clear the IMASKK bit. An interrupt signal on an edge-triggered pin can be acknowledged immediately after enabling the pin. An interrupt signal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that depends on the external load. Another way to avoid a false interrupt: 1. Configure the keyboard pins as outputs by setting the appropriate DDRA bits in the data direction register A. 2. Write 1s to the appropriate port A data register bits. 3. Enable the KBI pins by setting the appropriate KBIEx bits in the keyboard interrupt enable register.
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9.4 Wait Mode
The keyboard module remains active in wait mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of wait mode.
9.5 Stop Mode
The keyboard module remains active in stop mode. Clearing the IMASKK bit in the keyboard status and control register enables keyboard interrupt requests to bring the MCU out of stop mode.
9.6 Keyboard Module During Break Interrupts
The system integration module (SIM) controls whether the keyboard interrupt latch can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. To allow software to clear the keyboard interrupt latch during a break interrupt, write a 1 to the BCFE bit. If a latch is cleared during the break state, it remains cleared when the MCU exits the break state.
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Keyboard Interrupt Module (KBI)
Data Sheet 83
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Keyboard Interrupt Module (KBI)
To protect the latch during the break state, write a 0 to the BCFE bit. With BCFE at 0 (its default state), writing to the keyboard acknowledge bit (ACKK) in the keyboard status and control register during the break state has no effect.
9.7 Input/Output Registers
The following I/O registers control and monitor operation of the keyboard interrupt module: * * Keyboard interrupt status and control register (KBSCR) Keyboard interrupt enable register (KBIER)
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9.7.1 Keyboard Status and Control Register The keyboard status and control register (KBSCR): * * * * Flags keyboard interrupt requests Acknowledges keyboard interrupt requests Masks keyboard interrupt requests Controls keyboard interrupt triggering sensitivity
$001A Bit 7 Read: Write: Reset: 0 0 0 0 0 = Unimplemented 0 6 0 5 0 4 0 3 KEYF 2 0 ACKK 0 1 IMASKK 0 Bit 0 MODEK 0
Address:
Figure 9-4. Keyboard Status and Control Register (KBSCR) Bits 7-4 -- Not used These read-only bits always read as 0s. KEYF -- Keyboard Flag Bit This read-only bit is set when a keyboard interrupt is pending on port A or auto wakeup. Reset clears the KEYF bit. 1 = Keyboard interrupt pending 0 = No keyboard interrupt pending ACKK -- Keyboard Acknowledge Bit Writing a 1 to this write-only bit clears the keyboard interrupt request on port A and auto wakeup logic. ACKK always reads as 0. Reset clears ACKK.
Data Sheet 84 Keyboard Interrupt Module (KBI)
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Keyboard Interrupt Module (KBI) Input/Output Registers
IMASKK-- Keyboard Interrupt Mask Bit Writing a 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests on port A or auto wakeup. Reset clears the IMASKK bit. 1 = Keyboard interrupt requests masked 0 = Keyboard interrupt requests not masked MODEK -- Keyboard Triggering Sensitivity Bit This read/write bit controls the triggering sensitivity of the keyboard interrupt pins on port A and auto wakeup. Reset clears MODEK. 1 = Keyboard interrupt requests on falling edges and low levels 0 = Keyboard interrupt requests on falling edges only
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9.7.2 Keyboard Interrupt Enable Register The port A keyboard interrupt enable register (KBIER) enables or disables each port A pin or auto wakeup to operate as a keyboard interrupt input.
Address: $001B Bit 7 Read: Write: Reset: 0 0 6 AWUIE 0 5 KBIE5 0 4 KBIE4 0 3 KBIE3 0 2 KBIE2 0 1 KBIE1 0 Bit 0 KBIE0 0
= Unimplemented
Figure 9-5. Keyboard Interrupt Enable Register (KBIER) KBIE5-KBIE0 -- Port A Keyboard Interrupt Enable Bits Each of these read/write bits enables the corresponding keyboard interrupt pin on port A to latch interrupt requests. Reset clears the keyboard interrupt enable register. 1 = KBIx pin enabled as keyboard interrupt pin 0 = KBIx pin not enabled as keyboard interrupt pin NOTE: AWUIE bit is not used in conjunction with the keyboard interrupt feature. To see a description of this bit, see Section 4. Auto Wakeup Module (AWU).
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Keyboard Interrupt Module (KBI)
Data Sheet 85
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Keyboard Interrupt Module (KBI)
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Data Sheet 86 Keyboard Interrupt Module (KBI)
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Data Sheet -- MC68HC908QF4
Section 10. Low-Voltage Inhibit (LVI)
10.1 Introduction
This section describes the low-voltage inhibit (LVI) module, which monitors the voltage on the VDD pin and can force a reset when the VDD voltage falls below the LVI trip falling voltage, VTRIPF.
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10.2 Features
Features of the LVI module include: * * * * Programmable LVI reset Programmable power consumption Selectable LVI trip voltage Programmable stop mode operation
10.3 Functional Description
Figure 10-1 shows the structure of the LVI module. LVISTOP, LVIPWRD, LVDLVR, and LVIRSTD are user selectable options found in the configuration register (CONFIG1). See Section 5. Configuration Register (CONFIG).
VDD STOP INSTRUCTION LVISTOP FROM CONFIG FROM CONFIG LVIRSTD LVIPWRD FROM CONFIG LOW VDD DETECTOR VDD > LVITRIP = 0 VDD LVITRIP = 1 LVIOUT LVDLVR FROM CONFIG LVI RESET
Figure 10-1. LVI Module Block Diagram
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Low-Voltage Inhibit (LVI)
Data Sheet 87
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Low-Voltage Inhibit (LVI)
The LVI is enabled out of reset. The LVI module contains a bandgap reference circuit and comparator. Clearing the LVI power disable bit (LVIPWRD) enables the LVI to monitor VDD voltage. Clearing the LVI reset disable bit (LVIRSTD) enables the LVI module to generate a reset when VDD falls below a voltage, VTRIPF or VDTRIPF. Setting the LVI enable in stop mode bit (LVISTOP) enables the LVI to operate in stop mode. Setting the LVD or LVR trip point bit (LVDLVR) selects the LVD trip point voltage. The actual trip thresholds are specified in 17.5 DC Electrical Characteristics. Either trip level can be used as a detect or reset. NOTE: After a power-on reset, the LVI's default mode of operation is LVR trip voltage. If a higher trip voltage is desired, the user must set the LVDLVR bit to raise the trip point to the LVD voltage. If the user requires the higher trip voltage and sets the LVDLVR bit after power-on reset while the VDD supply is not above the VTRIPR for LVD mode, the microcontroller unit (MCU) will immediately go into reset. The next time the LVI releases the reset, the supply will be above the VTRIPR for LVD mode. Once an LVI reset occurs, the MCU remains in reset until VDD rises above a voltage, VTRIPR, which causes the MCU to exit reset. See Section 14. System Integration Module (SIM) for the reset recovery sequence. The output of the comparator controls the state of the LVIOUT flag in the LVI status register (LVISR) and can be used for polling LVI operation when the LVI reset is disabled. 10.3.1 Polled LVI Operation In applications that can operate at VDD levels below the VTRIPF level, software can monitor VDD by polling the LVIOUT bit. In the configuration register, the LVIPWRD bit must be cleared to enable the LVI module, and the LVIRSTD bit must be set to disable LVI resets. 10.3.2 Forced Reset Operation In applications that require VDD to remain above the VTRIPF level, enabling LVI resets allows the LVI module to reset the MCU when VDD falls below the VTRIPF level. In the configuration register, the LVIPWRD and LVIRSTD bits must be cleared to enable the LVI module and to enable LVI resets. 10.3.3 Voltage Hysteresis Protection Once the LVI has triggered (by having VDD fall below VTRIPF), the LVI will maintain a reset condition until VDD rises above the rising trip point voltage, VTRIPR. This prevents a condition in which the MCU is continually entering and exiting reset if VDD is approximately equal to VTRIPF. VTRIPR is greater than VTRIPF by the hysteresis voltage, VHYS.
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Data Sheet 88 Low-Voltage Inhibit (LVI)
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Low-Voltage Inhibit (LVI) LVI Status Register
10.3.4 LVI Trip Selection The LVDLVR bit in the configuration register selects whether the LVI is configured for LVD (low voltage detect) or LVR (low voltage reset) protection. The LVD trip voltage can be used as a low voltage warning. The LVR trip voltage will commonly be configured as a reset condition since it is very close to the minimum operating voltage of the device. The LVDLVR bit can be written to anytime so that battery applications can make use of the LVI as both a warning indicator and to generate a system reset. Polling and forced reset operation modes can be combined to take full advantage of LVD and LVR trip voltages selection. LVD (LVDLVR = 1) in polling mode (LVIRSTD = 1) can be used as a low voltage warning in a slowly and continuously falling VDD application (for example, battery applications). Once LVD has been identified, the part can be set to LVR (LVDLVR = 0) and reset enabled (LVIRSTD = 0). So, as VDD continues to fall the part will reset when LVR trip voltage is reached. Unlike other bits in CONFIG registers, LVIRSTD and LVDLVR bits are allowed to be written multiple times after reset. NOTE: The microcontroller is guaranteed to operate at a minimum supply voltage. The trip point (VTRIPF [LVD] or VTRIPF [LVR]) may be lower than this. See 17.5 DC Electrical Characteristics for the actual trip point voltages.
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10.4 LVI Status Register
The LVI status register (LVISR) indicates if the VDD voltage was detected below the VTRIPF level while LVI resets have been disabled.
Address: $FE0C Bit 7 Read: Write: Reset: 0 0 = Unimplemented 0 0 0 R 0 = Reserved 0 0 LVIOUT 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0 R
Figure 10-2. LVI Status Register (LVISR) LVIOUT -- LVI Output Bit This read-only flag becomes set when the VDD voltage falls below the VTRIPF trip voltage and is cleared when VDD voltage rises above VTRIPR. The difference in these threshold levels results in a hysteresis that prevents oscillation into and out of reset (see Table 10-1). Reset clears the LVIOUT bit.
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Low-Voltage Inhibit (LVI)
Data Sheet 89
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Low-Voltage Inhibit (LVI)
Table 10-1. LVIOUT Bit Indication
VDD VDD > VTRIPR VDD < VTRIPF VTRIPF < VDD < VTRIPR LVIOUT 0 1 Previous value
10.5 LVI Interrupts
The LVI module does not generate interrupt requests.
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10.6 Low-Power Modes
The STOP and WAIT instructions put the MCU in low power-consumption standby modes. 10.6.1 Wait Mode If enabled, the LVI module remains active in wait mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of wait mode. 10.6.2 Stop Mode When the LVIPWRD bit in the configuration register is cleared and the LVISTOP bit in the configuration register is set, the LVI module remains active in stop mode. If enabled to generate resets, the LVI module can generate a reset and bring the MCU out of stop mode.
Data Sheet 90 Low-Voltage Inhibit (LVI)
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Data Sheet -- MC68HC908QF4
Section 11. Oscillator Module (OSC)
11.1 Introduction
The oscillator module is used to provide a stable clock source for the microcontroller system and bus. The oscillator module generates two output clocks, BUSCLKX2 and BUSCLKX4. The BUSCLKX4 clock is used by the system integration module (SIM) and the computer operating properly module (COP). The BUSCLKX2 clock is divided by two in the SIM to be used as the bus clock for the microcontroller. Therefore the bus frequency will be one forth of the BUSCLKX4 frequency.
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11.2 Features
The oscillator has these four clock source options available: 1. Internal oscillator: An internally generated, fixed frequency clock, trimmable to 5%. This is the default option out of reset. 2. External oscillator: An external clock that can be driven directly into OSC1. 3. External RC: A built-in oscillator module (RC oscillator) that requires an external R connection only. The capacitor is internal to the chip. 4. External crystal: A built-in oscillator module (XTAL oscillator) that requires an external crystal or ceramic-resonator.
11.3 Functional Description
The oscillator contains these major subsystems: * * * * * 11.3.1 Internal Oscillator The internal oscillator circuit is designed for use with no external components to provide a clock source with tolerance less than 25% untrimmed. An 8-bit trimming register allows adjustment to a tolerance of less than 5%. The internal oscillator will generate a clock of 4.0 MHz typical (INTCLK) resulting in a bus speed (internal clock / 4) of 1.0 MHz. Internal oscillator circuit Internal or external clock switch control External clock circuit External crystal circuit External RC clock circuit
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Oscillator Module (OSC)
Data Sheet 91
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Oscillator Module (OSC)
PTA0/AD0/TCH0/KBI0 PTA1/AD1/TCH1/KBI1 DDRA PTA PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 M68HC08 CPU PTB0 PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 CLOCK GENERATOR (OSCILLATOR)
SYSTEM INTEGRATION MODULE SINGLE INTERRUPT MODULE BREAK MODULE POWER-ON RESET MODULE KEYBOARD INTERRUPT MODULE 16-BIT TIMER MODULE COP MODULE VCC MODE PLLEN DATA BS OP1 GND REXT XTAL1 XTAL0 UPCLK PFD
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8-BIT ADC
DDRB
PTB
MC68HC908QF4 4096 BYTES USER FLASH
128 BYTES RAM
MONITOR ROM
UHF TRANSMITTER
VDD POWER SUPPLY VSS
RST, IRQ: Pins have internal (about 30K Ohms) pull up PTA[0:5]: High current sink and source capability PTA[0:5]: Pins have programmable keyboard interrupt and pull up
Figure 11-1. Block Diagram Highlighting OSC Block and Pins
Data Sheet 92 Oscillator Module (OSC)
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Oscillator Module (OSC) Functional Description
Figure 11-3 shows how BUSCLKX4 is derived from INTCLK and, like the RC oscillator, OSC2 can output BUSCLKX4 by setting OSC2EN in PTAPUE register. See Section 13. Input/Output (I/O) Ports. 11.3.1.1 Internal Oscillator Trimming The 8-bit trimming register, OSCTRIM, allows a clock period adjust of +127 and -128 steps. Increasing OSCTRIM value increases the clock period. Trimming allows the internal clock frequency to be set to 4.0 MHz 5%. All devices are programmed with a trim value in a reserved FLASH location, $FFC0. This value can be copied from the FLASH to the OSCTRIM register ($0038) during reset initialization. Reset loads OSCTRIM with a default value of $80.
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WARNING:
Bulk FLASH erasure will set location $FFC0 to $FF and the factory programmed value will be lost.
11.3.1.2 Internal to External Clock Switching When external clock source (external OSC, RC, or XTAL) is desired, the user must perform the following steps: 1. For external crystal circuits only, OSCOPT[1:0] = 1:1: To help precharge an external crystal oscillator, set PTA4 (OSC2) as an output and drive high for several cycles. This may help the crystal circuit start more robustly. 2. Set CONFIG2 bits OSCOPT[1:0] according to 11.7 CONFIG2 Options. The oscillator module control logic will then set OSC1 as an external clock input and, if the external crystal option is selected, OSC2 will also be set as the clock output. 3. Create a software delay to wait the stabilization time needed for the selected clock source (crystal, resonator, RC) as recommended by the component manufacturer. A good rule of thumb for crystal oscillators is to wait 4096 cycles of the crystal frequency, i.e., for a 4-MHz crystal, wait approximately 1 msec. 4. After the manufacturer's recommended delay has elapsed, the ECGON bit in the OSC status register (OSCSTAT) needs to be set by the user software. 5. After ECGON set is detected, the OSC module checks for oscillator activity by waiting two external clock rising edges. 6. The OSC module then switches to the external clock. Logic provides a glitch free transition. 7. The OSC module first sets the ECGST bit in the OSCSTAT register and then stops the internal oscillator. NOTE: Once transition to the external clock is done, the internal oscillator will only be reactivated with reset. No post-switch clock monitor feature is implemented (clock does not switch back to internal if external clock dies).
Data Sheet Oscillator Module (OSC) 93
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Oscillator Module (OSC)
11.3.2 External Oscillator The external clock option is designed for use when a clock signal is available in the application to provide a clock source to the microcontroller. The OSC1 pin is enabled as an input by the oscillator module. The clock signal is used directly to create BUSCLKX4 and also divided by two to create BUSCLKX2. In this configuration, the OSC2 pin cannot output BUSCLKX4. So the OSC2EN bit in the port A pullup enable register will be clear to enable PTA4 I/O functions on the pin. 11.3.3 XTAL Oscillator
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The XTAL oscillator circuit is designed for use with an external low-frequency crystal or ceramic resonator to provide an accurate clock source. In this configuration, the OSC2 pin is dedicated to the external crystal circuit. The OSC2EN bit in the port A pullup enable register has no effect when this clock mode is selected. In its typical configuration, the XTAL oscillator is connected in a Pierce oscillator configuration, as shown in Figure 11-2. This figure shows only the logical representation of the internal components and may not represent actual circuitry. The oscillator configuration uses five components: * Crystal, X1 * Fixed capacitor, C1 * Tuning capacitor, C2 (can also be a fixed capacitor) * Feedback resistor, RB * Series resistor, RS
FROM SIM TO SIM BUSCLKX4 XTALCLK SIMOSCEN MCU OSC1 RB X1 OSC2 RS TO SIM BUSCLKX2 /2
C1
C2
Figure 11-2. XTAL Oscillator External Connections
Data Sheet 94 Oscillator Module (OSC) MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Oscillator Module (OSC) Oscillator Module Signals
11.3.4 RC Oscillator The RC oscillator circuit is designed for use with external R to provide a clock source with tolerance less than 25%. In its typical configuration, the RC oscillator requires two external components, one R and one C. In the MC68HLC908QF4, the capacitor is internal to the chip. The R value should have a tolerance of 1% or less, to obtain a clock source with less than 25% tolerance. The oscillator configuration uses one component, REXT. In this configuration, the OSC2 pin can be left in the reset state as PTA4. Or, the OSC2EN bit in the port A pullup enable register can be set to enable the OSC2 output function on the pin. Enabling the OSC2 output slightly increases the external RC oscillator frequency, fRCCLK.
OSCRCOPT FROM SIM INTCLK 0 BUSCLKX4 1 SIMOSCEN EXTERNAL RC EN OSCILLATOR RCCLK /2 BUSCLKX2 TO SIM TO SIM
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1 PTA4 I/O
0 MCU OSC1 VDD REXT PTA4/BUSCLKX4 (OSC2)
PTA4 OSC2EN
See Section 17. Electrical Specifications for component value requirements.
Figure 11-3. RC Oscillator External Connections
11.4 Oscillator Module Signals
The following paragraphs describe the signals that are inputs to and outputs from the oscillator module. 11.4.1 Crystal Amplifier Input Pin (OSC1) The OSC1 pin is either an input to the crystal oscillator amplifier, an input to the RC oscillator circuit, or an external clock source.
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Oscillator Module (OSC)
Data Sheet 95
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Oscillator Module (OSC)
For the internal oscillator configuration, the OSC1 pin can assume other functions according to Table 1-1. Pin Functions. 11.4.2 Crystal Amplifier Output Pin (OSC2/PTA4/BUSCLKX4) For the XTAL oscillator device, the OSC2 pin is the crystal oscillator inverting amplifier output. For the external clock option, the OSC2 pin is dedicated to the PTA4 I/O function. The OSC2EN bit has no effect. For the internal oscillator or RC oscillator options, the OSC2 pin can assume other functions according to Table 1-1. Pin Functions, or the output of the oscillator clock (BUSCLKX4). Table 11-1. OSC2 Pin Function
Option XTAL oscillator External clock Internal oscillator or RC oscillator OSC2 Pin Function Inverting OSC1 PTA4 I/O Controlled by OSC2EN bit in PTAPUE register OSC2EN = 0: PTA4 I/O OSC2EN = 1: BUSCLKX4 output
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11.4.3 Oscillator Enable Signal (SIMOSCEN) The SIMOSCEN signal comes from the system integration module (SIM) and enables/disables either the XTAL oscillator circuit, the RC oscillator, or the internal oscillator. 11.4.4 XTAL Oscillator Clock (XTALCLK) XTALCLK is the XTAL oscillator output signal. It runs at the full speed of the crystal (fXCLK) and comes directly from the crystal oscillator circuit. Figure 11-2 shows only the logical relation of XTALCLK to OSC1 and OSC2 and may not represent the actual circuitry. The duty cycle of XTALCLK is unknown and may depend on the crystal and other external factors. Also, the frequency and amplitude of XTALCLK can be unstable at start up. 11.4.5 RC Oscillator Clock (RCCLK) RCCLK is the RC oscillator output signal. Its frequency is directly proportional to the time constant of external R and internal C. Figure 11-3 shows only the logical relation of RCCLK to OSC1 and may not represent the actual circuitry.
Data Sheet 96 Oscillator Module (OSC)
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Oscillator Module (OSC) Low Power Modes
11.4.6 Internal Oscillator Clock (INTCLK) INTCLK is the internal oscillator output signal. Its nominal frequency is fixed to 4.0 MHz, but it can be also trimmed using the oscillator trimming feature of the OSCTRIM register (see 11.3.1.1 Internal Oscillator Trimming). 11.4.7 Oscillator Out 2 (BUSCLKX4) BUSCLKX4 is the same as the input clock (XTALCLK, RCCLK, or INTCLK). This signal is driven to the SIM module and is used to determine the COP cycles. 11.4.8 Oscillator Out (BUSCLKX2)
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The frequency of this signal is equal to half of the BUSCLKX4, this signal is driven to the SIM for generation of the bus clocks used by the CPU and other modules on the MCU. BUSCLKX2 will be divided again in the SIM and results in the internal bus frequency being one fourth of either the XTALCLK, RCCLK, or INTCLK frequency.
11.5 Low Power Modes
The WAIT and STOP instructions put the MCU in low-power consumption standby modes. 11.5.1 Wait Mode The WAIT instruction has no effect on the oscillator logic. BUSCLKX2 and BUSCLKX4 continue to drive to the SIM module. 11.5.2 Stop Mode The STOP instruction disables either the XTALCLK, the RCCLK, or INTCLK output, hence BUSCLKX2 and BUSCLKX4.
11.6 Oscillator During Break Mode
The oscillator continues to drive BUSCLKX2 and BUSCLKX4 when the device enters the break state.
11.7 CONFIG2 Options
Two CONFIG2 register options affect the operation of the oscillator module: OSCOPT1 and OSCOPT0. All CONFIG2 register bits will have a default configuration. Refer to Section 5. Configuration Register (CONFIG) for more information on how the CONFIG2 register is used.
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Oscillator Module (OSC)
Data Sheet 97
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Oscillator Module (OSC)
Table 11-2 shows how the OSCOPT bits are used to select the oscillator clock source.
Table 11-2. Oscillator Modes
OSCOPT1 0 0 1 1 OSCOPT0 0 1 0 1 Oscillator Modes Internal Oscillator External Oscillator External RC External Crystal
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11.8 Input/Output (I/O) Registers
The oscillator module contains these two registers: 1. Oscillator status register (OSCSTAT) 2. Oscillator trim register (OSCTRIM) 11.8.1 Oscillator Status Register The oscillator status register (OSCSTAT) contains the bits for switching from internal to external clock sources.
Address: $0036 Bit 7 Read: Write: Reset: R 0 R 6 R 0 = Reserved 5 R 0 4 R 0 3 R 0 = Unimplemented 2 R 0 1 ECGON 0 Bit 0 ECGST 0
Figure 11-4. Oscillator Status Register (OSCSTAT) ECGON -- External Clock Generator On Bit This read/write bit enables external clock generator, so that the switching process can be initiated. This bit is forced low during reset. This bit is ignored in monitor mode with the internal oscillator bypassed. 1 = External clock generator enabled 0 = External clock generator disabled ECGST -- External Clock Status Bit This read-only bit indicates whether or not an external clock source is engaged to drive the system clock. 1 = An external clock source engaged 0 = An external clock source disengaged
Data Sheet 98 Oscillator Module (OSC)
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Oscillator Module (OSC) Input/Output (I/O) Registers
11.8.2 Oscillator Trim Register (OSCTRIM)
Address: $0038 Bit 7 Read: Write: Reset: TRIM7 1 6 TRIM6 0 5 TRIM5 0 4 TRIM4 0 3 TRIM3 0 2 TRIM2 0 1 TRIM1 0 Bit 0 TRIM0 0
Figure 11-5. Oscillator Trim Register (OSCTRIM) TRIM7-TRIM0 -- Internal Oscillator Trim Factor Bits These read/write bits change the size of the internal capacitor used by the internal oscillator. By measuring the period of the internal clock and adjusting this factor accordingly, the frequency of the internal clock can be fine tuned. Increasing (decreasing) this factor by one increases (decreases) the period by approximately 0.2% of the untrimmed period (the period for TRIM = $80). The trimmed frequency is guaranteed not to vary by more than 5% over the full specified range of temperature and voltage. The reset value is $80, which sets the frequency to 4.0 MHz (1.0 MHz bus speed) 25%.
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MC68HC908QF4 -- Rev. 1.0 MOTOROLA Oscillator Module (OSC)
Data Sheet 99
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Oscillator Module (OSC)
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Data Sheet 100 Oscillator Module (OSC)
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Data Sheet -- MC68HC908QF4
Section 12. PLL Tuned UHF Transmitter Module
12.1 Introduction
This section describes the integrated radio frequency (RF) module. This module integrates an ultra high frequency (UHF) transmitter offering these key features: * Switchable frequency bands: 315, 434, and 868 MHz On/off keying (OOK) and frequency shift keying (FSK) modulation Adjustable output power range Fully integrated voltage-controlled oscillator (VCO) Supply voltage range: 1.9 to 3.6 V Very low standby current: 0.1 nA @ TA = 25C Low supply voltage shutdown Data clock output for microcontroller Low external component count
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* * * * * * * *
Architecture of the module is described in Figure 12-1.
BAND
VCO
REXT
VCC GND FIRST ORDER ENABLE ENABLE_FSK DATA_OOK DATA_FSK
PFD
/32
/2
PA
RFOUT
MODE DATA ENABLE CONTROL
GNDRF
XCO
/64
DRIVER
DATACLK
CFSK
XTAL0
XTAL1
Figure 12-1. Simplified Integrated RF Module Block Diagram
MC68HC908QF4 -- Rev. 1.0 MOTOROLA PLL Tuned UHF Transmitter Module
Data Sheet 101
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PLL Tuned UHF Transmitter Module
PTA0/AD0/TCH0/KBI0 PTA1/AD1/TCH1/KBI1 DDRA PTA PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 M68HC08 CPU PTB0 PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 CLOCK GENERATOR (OSCILLATOR)
SYSTEM INTEGRATION MODULE SINGLE INTERRUPT MODULE BREAK MODULE POWER-ON RESET MODULE KEYBOARD INTERRUPT MODULE 16-BIT TIMER MODULE COP MODULE VCC MODE PLLEN DATA BS OP1 GND REXT XTAL1 XTAL0 UPCLK PFD
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8-BIT ADC
DDRB
PTB
MC68HC908QF4 4096 BYTES USER FLASH
128 BYTES RAM
MONITOR ROM
UHF TRANSMITTER
VDD POWER SUPPLY VSS
RST, IRQ: Pins have internal (about 30K Ohms) pull up PTA[0:5]: High current sink and source capability PTA[0:5]: Pins have programmable keyboard interrupt and pull up
Figure 12-2. Block Diagram Highlighting PLL Tuned UHF Transmitter Block and Pins
Data Sheet 102 PLL Tuned UHF Transmitter Module
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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PLL Tuned UHF Transmitter Module Transmitter Functional Description
12.2 Transmitter Functional Description
The transmitter is a phase-locked loop (PLL) tuned low-power UHF transmitter. The different modes of operation are controlled by the microcontroller through several digital input pins. The power supply voltage ranges from 1.9 V to 3.6 V allowing operation with a single lithium cell.
12.3 Phase-Lock Loop (PLL) and Local Oscillator
The VCO is a completely integrated relaxation oscillator. The phase frequency detector (PFD) and the loop filter are fully integrated.The exact output frequency is equal to:
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fRFOUT = fXTAL x PLL divider ratio The frequency band of operation is selected through the BAND pin. Table 12-1 provides details for each frequency band selection. Table 12-1. Frequency Band Selection and Associated Divider Ratios
BAND Input Level High 434 13.56 Low 868 64 Frequency Band (MHz) 315 32 PLL Divider Ratio Crystal Oscillator Frequency (MHz) 9.84
An out-of-lock function is performed by monitoring the internal PFD output voltage. When it exceeds its limits, the RF output stage is disabled.
12.4 RF Output Stage
The output stage is a single-ended square wave switched current source. Harmonics will be present in the output current drive. Their radiated absolute level depends on the antenna characteristics and output power. Typical application demonstrates compliance to European Telecommunications Standards Institute (ETSI) standard. A resistor REXT connected to the REXT pin controls the output power allowing a tradeoff between radiated power and current consumption. The output voltage is internally clamped to: VCC 2 VBE (typically VCC 1.5 V @ TA = 25C).
MC68HC908QF4 -- Rev. 1.0 MOTOROLA PLL Tuned UHF Transmitter Module
Data Sheet 103
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PLL Tuned UHF Transmitter Module
12.5 Modulation
If a low-logic level is applied on pin MODE, then the on/off keying (OOK) modulation is selected. This modulation is performed by switching on/off the RF output stage. The logic level applied on pin DATA controls the output stage state: DATA = 0 output stage off DATA = 1 output stage on If a high-logic level is applied on pin MODE, then frequency shift keying (FSK) modulation is selected. This modulation is achieved by modulating the frequency of the reference oscillator. This frequency change is performed by switching the external crystal load capacitor. The logic level applied on pin DATA controls the internal switch connected to pin CFSK: DATA = 0 switch off DATA = 1 switch on In case of Figure 12-6, where the two capacitors C6 and C9 are in series: DATA = 0 leads to the high value of the carrier frequency DATA = 1 leads to the low value of the carrier frequency This crystal pulling solution implies that the RF output frequency deviation equals the crystal frequency deviation multipled by the PLL divider ratio (see Table 12-1).
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12.6 Microcontroller Interfaces
Four digital input pins (ENABLE, DATA, BAND, and MODE) enable the circuit to be controlled by a microcontroller. It is recommended to configure the band frequency and the modulation type before enabling the circuit. In a typical application the input pins BAND and MODE are hardwired. One digital output (DATACLK) provides the microcontroller a reference frequency for data clocking. This frequency is equal to the crystal oscillator frequency divided by 64 (see Table 12-2). Table 12-2. DATACLK Frequency versus Crystal Oscillator Frequency
Crystal Oscillator Frequency (MHz) 9.84 13.56 DATACLK Frequency (kHz) 154 212
Data Sheet 104 PLL Tuned UHF Transmitter Module
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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PLL Tuned UHF Transmitter Module State Machine
12.7 State Machine
Figure 12-3 details the main state machine.
POWER ON AND ENABLE = 0
STATE 1 STANDBY MODE
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ENABLE = 0
ENABLE = 1
ENABLE = 0
STATE 2 PLL ENABLED BUT OUT OF LOCK-IN RANGE
STATE 6 SHUTDOWN MODE
PLL IN LOCK-IN RANGE
PLL OUT OF LOCK-IN RANGE
VBattery < VShutdoown
STATE 3 PLL ACQUISITION, READY TO TRANSMIT
DATA
STATE 4 TRANSMISSION MODE
PLL IN LOCK-IN RANGE
PLL OUT OF LOCK-IN RANGE
STATE 5 PLL OUT OF LOCK-IN RANGE
Figure 12-3. Main State Machine
MC68HC908QF4 -- Rev. 1.0 MOTOROLA PLL Tuned UHF Transmitter Module
Data Sheet 105
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PLL Tuned UHF Transmitter Module
State 1 The circuit is in standby mode and draws only a leakage current from the power supply. State 2 In this state, the PLL is enabled but out of the lock-in range. Therefore the RF output stage is switched off preventing any data transmission. Data clock is available on pin DATACLK. In normal operation, this state is transitional. State 3 In this state, the PLL is within the lock-in range. If t < tPLL_Lock_In, then the PLL can still be in acquisition mode. If t tPLL_Lock_In, then the PLL is locked. The circuit is ready to transmit in band and is waiting for the first data (see Figure 12-4). State 4 A rising edge on pin DATA starts the transmission. Data entered on pin DATA are output on pin RFOUT. The modulation is the one selected through the level applied on pin MODE. State 5 An out-of-lock condition has been detected. The RF output stage is switched off preventing any data transmission. Data clock is available on pin DATACLK. State 6 When the supply voltage falls below the shutdown voltage threshold (VSDWN) the whole circuit is switched off. Applying a low level on pin ENABLE is the only condition to get out of this state. Figure 12-4 shows the waveforms of the main signals for a typical application cycle
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ENABLE
DATACLK tDATACLK_Settling tPLL_Lock_In DATA SEE NOTE
MODE = 0, OOK MODULATION RFOUT MODE = 1, FSK MODULATION STATE 1 STATE 2 STATE 3
fCarrier fCarrier1 fCarrier2
fCarrier fCarrier1 fCarrier2 STATE 1
STATE 4
Note: PLL locked, circuit ready to tramsmit in band.
Figure 12-4. Signals, Waveforms, and Timing Definitions
Data Sheet 106 PLL Tuned UHF Transmitter Module MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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PLL Tuned UHF Transmitter Module Power Management
12.8 Power Management
When the battery voltage falls below the shutdown voltage threshold (VSDWN) the whole circuit is switched off. NOTE: After this shutdown, the circuit is latched until a low level is applied on pin ENABLE (see state 6 under 12.7 State Machine).
12.9 Data Clock
When the data clock starts, the high-to-low ratio may be uneven. Similarly the clock is switched off asynchronously so the last period length is not guaranteed.
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12.10 Application Information
This subsection provides application information for the usage of the UHF transmitter module. 12.10.1 Application Schematics in OOK and FSK Modulation Figure 12-5 and Figure 12-6 show application schematics in OOK and FSK modulation for the 315-MHz and 434-MHz frequency bands. For 868-MHz band application, the input pin BAND must be wired to GND. See component description in Table 12-4 and Table 12-5.
VCC VCC TO MCU
DATACLK DATA BAND GND XTAL1
MODE ENABLE VCC GNDRF RFOUT VCC CFSK NC MATCHING NETWORK ANTENNA
Y1
XTAL0 REXT
C6
R2
C7
C8
NC = NO CONNECTION
Figure 12-5. Application Schematic in OOK Modulation, 315-MHz and 434-MHz Frequency Bands
MC68HC908QF4 -- Rev. 1.0 MOTOROLA PLL Tuned UHF Transmitter Module Data Sheet 107
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PLL Tuned UHF Transmitter Module
VCC VCC TO MCU
DATACLK DATA BAND GND XTAL1
MODE ENABLE VCC GNDRF RFOUT VCC CFSK MATCHING NETWORK ANTENNA
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C6
Y1
XTAL0 REXT
C9
R2
C7
C8
Figure 12-6. Application Schematic in FSK Modulation, 315-MHz and 434-MHz Frequency Bands Table 12-3. Component Description
Component Function Value 315-MHz band: 9.84, see Table 12-5 Y1 Crystal 434-MHz band: 13.56, see Table 12-5 868-MHz band: 13.56, see Table 12-5 R2 RF output level setting resistor (REXT) Crystal load capacitor FSK modulation: 22 C7 Power supply decoupling capacitor C8 C9 Crystal pulling capacitor for FSK modulation only 100 See Table 12-5 pF pF 10 pF nF 12 OOK modulation: 18 C6 Unit MHz MHz MHz k pF
Data Sheet 108 PLL Tuned UHF Transmitter Module
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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PLL Tuned UHF Transmitter Module Application Information
A example of crystal reference is: Tokyo Denpa TTS-3B 13568.750 kHz, see Table 12-4. Table 12-4. Recommended Crystal Characteristics (SMD Ceramic Package)
Parameter Load capacitance Motional capacitance Static capacitance Loss resistance Value 20 6.7 2 40 Unit pF fF pF W
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Table 12-5. Crystal Pulling Capacitor Value versus Carrier Frequency Total Deviation
Carrier Frequency (MHz) Carrier Frequency Total Deviation (kHz) 40 434 70 100 80 868 140 200 Capacitor Value (pF) 18 10 6.8 18 10 6.8
12.10.2 Complete Application Schematic Figure 12-7 gives a complete application schematic using the Motorola MC68HC908RF2. OOK modulation is selected, fCarrier = 433.92 MHz.
MC68HC908QF4 -- Rev. 1.0 MOTOROLA PLL Tuned UHF Transmitter Module
Data Sheet 109
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PLL Tuned UHF Transmitter Module
SW1
SW2
PTB5 PTA4/OSC2/KBI4
NC PTA5/OSC1/KBI5
PTB4
PTB6
PTB7
NC
VBATT 26 32 31 30 29 28 27 25
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DATACLK
PTA3/RST/KBI3 PTA2/IRQ/KBI2/TCK PTB3 PTB2 PTA1/TCH1/KBI1 GND
1 2 3 4 MC68HC908QF4 5 6 7 8 10 11 12 13 14 15 16 9
24 23 22 21 20 19 18 17
VDD VSS PTB0 PTB1 PTA0/TCH0/KBI0 DATACLK DATA BAND DATACLK DATA VBATT ENABLE C3 10 nF
DATA C10 18 pF
XTAL1 Y1 13.56 MHz XTAL0
ENABLE
R2 12 K ENABLE
VBATT C9 2.2 pF C6 10 nF C5 100 pF
Figure 12-7. Complete Application Schematic in OOK Modulation, 434-MHz Frequency Band
Data Sheet 110 PLL Tuned UHF Transmitter Module
GNDDRF
RFOUT
MODE
CFSK VCC
REXT
VCC
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Data Sheet -- MC68HC908QF4
Section 13. Input/Output (I/O) Ports
13.1 Introduction
The MC68HC908QF4 has thirteen bidirectional pins and one input only pin. All I/O pins are programmable as inputs or outputs. NOTE:
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Connect any unused I/O pins to an appropriate logic level, either VDD or VSS. Although the I/O ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage. Figure 13-1 provides a summary of the I/O registers.
Addr. $0000
Register Name Port A Data Register (PTA) See page 112. Port B Data Register (PTB) See page 115. Data Direction Register A (DDRA) See page 113. Data Direction Register B (DDRB) See page 115. Port A Input Pullup Enable Register (PTAPUE) See page 114. Port B Input Pullup Enable Register (PTBPUE) See page 116. Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset:
Bit 7 R
6 AWUL
5 PTA5
4 PTA4
3 PTA3
2 PTA2
1 PTA1
Bit 0 PTA0
Unaffected by reset PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0
$0001
Unaffected by reset R 0 DDRB7 0 OSC2EN 0 PTBPUE7 0 R 0 PTBPUE6 0 = Reserved R 0 DDRB6 0 DDRA5 0 DDRB5 0 PTAPUE5 0 PTBPUE5 0 DDRA4 0 DDRB4 0 PTAPUE4 0 PTBPUE4 0 DDRA3 0 DDRB3 0 PTAPUE3 0 PTBPUE3 0 = Unimplemented 0 0 DDRB2 0 PTAPUE2 0 PTBPUE2 0 DDRA1 0 DDRB1 0 PTAPUE1 0 PTBPUE1 0 DDRA0 0 DDRB0 0 PTAPUE0 0 PTBPUE0 0
$0004
$0005
$000B
$000C
Figure 13-1. I/O Port Register Summary
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Input/Output (I/O) Ports
Data Sheet 111
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Input/Output (I/O) Ports
13.2 Port A
Port A is a 6-bit special function port that shares all six of its pins with the keyboard interrupt (KBI) module (see Section 9. Keyboard Interrupt Module (KBI)). Each port A pin also has a software configurable pullup device if the corresponding port pin is configured as an input port. NOTE: PTA2 is input only. When the IRQ function is enabled in the configuration register 2 (CONFIG2), bit 2 of the port A data register (PTA) will always read a 0. In this case, the BIH and BIL instructions can be used to read the logic level on the PTA2 pin. When the IRQ function is disabled, these instructions will behave as if the PTA2 pin is a logic 1. However, reading bit 2 of PTA will read the actual logic level on the pin. 13.2.1 Port A Data Register The port A data register (PTA) contains a data latch for each of the six port A pins.
Address: $0000 Bit 7 Read: Write: Reset: Additional Functions: R = Reserved KBI5 R 6 AWUL 5 PTA5 4 PTA4 3 PTA3 2 PTA2 1 PTA1 Bit 0 PTA0
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Unaffected by reset KBI4 KBI3 KBI2 KBI1 KBI0
= Unimplemented
Figure 13-2. Port A Data Register (PTA) PTA[5:0] -- Port A Data Bits These read/write bits are software programmable. Data direction of each port A pin is under the control of the corresponding bit in data direction register A. Reset has no effect on port A data. AWUL -- Auto Wakeup Latch Data Bit This is a read-only bit which has the value of the auto wakeup interrupt request latch. The wakeup request signal is generated internally (see Section 4. Auto Wakeup Module (AWU)). There is no PTA6 port nor any of the associated bits such as PTA6 data register, pullup enable or direction. KBI[5:0] -- Port A Keyboard Interrupts The keyboard interrupt enable bits, KBIE5-KBIE0, in the keyboard interrupt control enable register (KBIER) enable the port A pins as external interrupt pins (see Section 9. Keyboard Interrupt Module (KBI)).
Data Sheet 112 Input/Output (I/O) Ports
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Input/Output (I/O) Ports Port A
13.2.2 Data Direction Register A Data direction register A (DDRA) determines whether each port A pin is an input or an output. Writing a 1 to a DDRA bit enables the output buffer for the corresponding port A pin; a 0 disables the output buffer.
Address: $0004 Bit 7 Read: Write: Reset: R 0 R 6 R 0 = Reserved 5 DDRA5 0 4 DDRA4 0 3 DDRA3 0 2 0 0 1 DDRA1 0 Bit 0 DDRA0 0
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= Unimplemented
Figure 13-3. Data Direction Register A (DDRA) DDRA[5:0] -- Data Direction Register A Bits These read/write bits control port A data direction. Reset clears DDRA[5:0], configuring all port A pins as inputs. 1 = Corresponding port A pin configured as output 0 = Corresponding port A pin configured as input NOTE: Avoid glitches on port A pins by writing to the port A data register before changing data direction register A bits from 0 to 1. Figure 13-4 shows the port A I/O logic.
READ DDRA ($0004) PTAPUEx WRITE DDRA ($0004) INTERNAL DATA BUS RESET WRITE PTA ($0000) PTAx PTAx DDRAx 30 k
READ PTA ($0000)
TO KEYBOARD INTERRUPT CIRCUIT
Figure 13-4. Port A I/O Circuit NOTE: Figure 13-4 does not apply to PTA2 When DDRAx is a 1, reading address $0000 reads the PTAx data latch. When DDRAx is a 0, reading address $0000 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit.
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Input/Output (I/O) Ports Data Sheet 113
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Input/Output (I/O) Ports
13.2.3 Port A Input Pullup Enable Register The port A input pullup enable register (PTAPUE) contains a software configurable pullup device for each if the six port A pins. Each bit is individually configurable and requires the corresponding data direction register, DDRAx, to be configured as input. Each pullup device is automatically and dynamically disabled when its corresponding DDRAx bit is configured as output.
Address: $000B Bit 7 Read: Write: Reset: OSC2EN 0 0 6 5 PTAPUE5 0 4 PTAPUE4 0 3 PTAPUE3 0 2 PTAPUE2 0 1 PTAPUE1 0 Bit 0 PTAPUE0 0
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= Unimplemented
Figure 13-5. Port A Input Pullup Enable Register (PTAPUE)
OSC2EN -- Enable PTA4 on OSC2 Pin
This read/write bit configures the OSC2 pin function when internal oscillator or RC oscillator option is selected. This bit has no effect for the XTAL or external oscillator options. 1 = OSC2 pin outputs the internal or RC oscillator clock (BUSCLKX4) 0 = OSC2 pin configured for PTA4 I/O, having all the interrupt and pullup functions PTAPUE[5:0] -- Port A Input Pullup Enable Bits These read/write bits are software programmable to enable pullup devices on port A pins. 1 = Corresponding port A pin configured to have internal pull if its DDRA bit is set to 0 0 = Pullup device is disconnected on the corresponding port A pin regardless of the state of its DDRA bit Table 13-1 summarizes the operation of the port A pins. Table 13-1. Port A Pin Functions
PTAPUE Bit 1 0 X DDRA Bit 0 0 1 PTA Bit X(1) X X I/O Pin Mode Input, VDD(2) Input, Hi-Z(4) Output Accesses to DDRA Read/Write DDRA5-DDRA0 DDRA5-DDRA0 DDRA5-DDRA0 Accesses to PTA Read Pin Pin PTA5-PTA0 Write PTA5-PTA0(3) PTA5-PTA0(3) PTA5-PTA0(5)
1. X = don't care 2. I/O pin pulled to VDD by internal pullup. 3. Writing affects data register, but does not affect input. 4. Hi-Z = high impedance 5. Output does not apply to PTA2
Data Sheet 114 Input/Output (I/O) Ports
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Input/Output (I/O) Ports Port B
13.3 Port B
Port B is an 8-bit general purpose I/O port. 13.3.1 Port B Data Register The port B data register (PTB) contains a data latch for each of the eight port B pins.
Address: $0001 Bit 7 6 PTB6 5 PTB5 4 PTB4 3 PTB3 2 PTB2 1 PTB1 Bit 0 PTB0 Read: Write: Reset:
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PTB7
Unaffected by reset
Figure 13-6. Port B Data Register (PTB) PTB[7:0] -- Port B Data Bits These read/write bits are software programmable. Data direction of each port B pin is under the control of the corresponding bit in data direction register B. Reset has no effect on port B data. 13.3.2 Data Direction Register B Data direction register B (DDRB) determines whether each port B pin is an input or an output. Writing a 1 to a DDRB bit enables the output buffer for the corresponding port B pin; a 0 disables the output buffer.
Address: $0005 Bit 7 Read: Write: Reset: DDRB7 0 6 DDRB6 0 5 DDRB5 0 4 DDRB4 0 3 DDRB3 0 2 DDRB2 0 1 DDRB1 0 Bit 0 DDRB0 0
Figure 13-7. Data Direction Register B (DDRB) DDRB[7:0] -- Data Direction Register B Bits These read/write bits control port B data direction. Reset clears DDRB[7:0], configuring all port B pins as inputs. 1 = Corresponding port B pin configured as output 0 = Corresponding port B pin configured as input NOTE: Avoid glitches on port B pins by writing to the port B data register before changing data direction register B bits from 0 to 1. Figure 13-8 shows the port B I/O logic.
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Input/Output (I/O) Ports
Data Sheet 115
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Input/Output (I/O) Ports
READ DDRB ($0005) PTBPUEx WRITE DDRB ($0005) INTERNAL DATA BUS RESET WRITE PTB ($0001) PTBx PTBx DDRBx 30 k
READ PTB ($0001)
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Figure 13-8. Port B I/O Circuit When DDRBx is a 1, reading address $0001 reads the PTBx data latch. When DDRBx is a 0, reading address $0001 reads the voltage level on the pin. The data latch can always be written, regardless of the state of its data direction bit. Table 13-2 summarizes the operation of the port B pins. Table 13-2. Port B Pin Functions
DDRB Bit 0 1 PTB Bit X(1) X I/O Pin Mode Input, Hi-Z(2) Output Accesses to DDRB Read/Write DDRB7-DDRB0 DDRB7-DDRB0 Accesses to PTB Read Pin Pin Write PTB7-PTB0(3) PTB7-PTB0
1. X = don't care 2. Hi-Z = high impedance 3. Writing affects data register, but does not affect the input.
13.3.3 Port B Input Pullup Enable Register The port B input pullup enable register (PTBPUE) contains a software configurable pullup device for each of the eight port B pins. Each bit is individually configurable and requires the corresponding data direction register, DDRBx, be configured as input. Each pullup device is automatically and dynamically disabled when its corresponding DDRBx bit is configured as output.
Address: $000C Bit 7 Read: Write: Reset: PTBPUE7 6 PTBPUE6 5 PTBPUE5 4 PTBPUE4 3 PTBPUE3 2 PTBPUE2 1 PTBPUE2 Bit 0 PTBPUE0
0
0
0
0
0
0
0
0
Figure 13-9. Port B Input Pullup Enable Register (PTBPUE)
Data Sheet 116 Input/Output (I/O) Ports
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Input/Output (I/O) Ports Port B
PTBPUE[7:0] -- Port B Input Pullup Enable Bits These read/write bits are software programmable to enable pullup devices on port B pins 1 = Corresponding port B pin configured to have internal pull if its DDRB bit is set to 0 0 = Pullup device is disconnected on the corresponding port B pin regardless of the state of its DDRB bit. Table 13-3 summarizes the operation of the port B pins. Table 13-3. Port B Pin Functions
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PTBPUE Bit 1 0 X 1. 2. 3. 4.
DDRB Bit 0 0 1
PTB Bit X(1) X X
I/O Pin Mode Input, VDD(2) Input, Hi-Z(4) Output
Accesses to DDRB Read/Write DDRB7-DDRB0 DDRB7-DDRB0 DDRB7-DDRB0
Accesses to PTB Read Pin Pin PTB7-PTB0 Write PTB7-PTB0(3) PTB7-PTB0(3) PTB7-PTB0
X = don't care I/O pin pulled to VDD by internal pullup. Writing affects data register, but does not affect input. Hi-Z = high impedance
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Input/Output (I/O) Ports
Data Sheet 117
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Input/Output (I/O) Ports
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Data Sheet 118 Input/Output (I/O) Ports
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Data Sheet -- MC68HC908QF4
Section 14. System Integration Module (SIM)
14.1 Introduction
This section describes the system integration module (SIM), which supports up to 24 external and/or internal interrupts. Together with the central processor unit (CPU), the SIM controls all microcontroller unit (MCU) activities. A block diagram of the SIM is shown in Figure 14-1. Figure 14-2 is a summary of the SIM I/O registers. The SIM is a system state controller that coordinates CPU and exception timing. The SIM is responsible for: * Bus clock generation and control for CPU and peripherals - Stop/wait/reset/break entry and recovery - Internal clock control Master reset control, including power-on reset (POR) and computer operating properly (COP) timeout Interrupt control: - Acknowledge timing - Arbitration control timing - Vector address generation CPU enable/disable timing
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* *
*
14.2 RST and IRQ Pins Initialization
RST and IRQ pins come out of reset as PTA3 and PTA2 respectively. RST and IRQ functions can be activated by programing CONFIG2 accordingly. Refer to Section 5. Configuration Register (CONFIG).
MC68HC908QF4 -- Rev. 1.0 MOTOROLA System Integration Module (SIM)
Data Sheet 119
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System Integration Module (SIM)
MODULE STOP MODULE WAIT STOP/WAIT CONTROL CPU STOP (FROM CPU) CPU WAIT (FROM CPU) SIMOSCEN (TO OSCILLATOR) SIM COUNTER COP CLOCK
BUSCLKX4 (FROM OSCILLATOR) BUSCLKX2 (FROM OSCILLATOR) /2 VDD CLOCK CONTROL CLOCK GENERATORS INTERNAL CLOCKS
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INTERNAL PULL-UP
RESET PIN LOGIC
POR CONTROL RESET PIN CONTROL SIM RESET STATUS REGISTER MASTER RESET CONTROL
ILLEGAL OPCODE (FROM CPU) ILLEGAL ADDRESS (FROM ADDRESS MAP DECODERS) COP TIMEOUT (FROM COP MODULE) LVI RESET (FROM LVI MODULE) FORCED MON MODE ENTRY (FROM MENRST MODULE)
RESET
INTERRUPT CONTROL AND PRIORITY DECODE
INTERRUPT SOURCES CPU INTERFACE
Figure 14-1. SIM Block Diagram Table 14-1. Signal Name Conventions
Signal Name BUSCLKX4 BUSCLKX2 Address bus Data bus PORRST IRST R/W Description Buffered clock from the internal, RC or XTAL oscillator circuit. The BUSCLKX4 frequency divided by two. This signal is again divided by two in the SIM to generate the internal bus clocks (bus clock = BUSCLKX4 / 4). Internal address bus Internal data bus Signal from the power-on reset module to the SIM Internal reset signal Read/write signal
Data Sheet 120 System Integration Module (SIM)
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System Integration Module (SIM) SIM Bus Clock Control and Generation
Addr. $FE00
Register Name Break Status Register Read: (BSR) Write: See page 161. Reset:
Bit 7 R 0
6 R 0
5 R 0
4 R 0
3 R 0
2 R 0
1 SBSW Note 1 0
Bit 0 R 0
1. Writing a 0 clears SBSW. SIM Reset Status Register (SRSR) See page 135. Reserved Break Flag Control Read: Register (BFCR) Write: See page 136. Reset: Interrupt Status Register 1 (INT1) Write: See page 130. Reset: Interrupt Status Register 2 Read: (INT2) Write: See page 131. Reset: Read: Read: Write: POR: 1 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R POR PIN COP ILOP ILAD MODRST LVI 0
$FE01 $FE02
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$FE03
BCFE 0 0 R 0 IF14 R 0 0 R 0
R
R
R
R
R
R
R
IF5 R 0 0 R 0 0 R 0
IF4 R 0 0 R 0 0 R 0
IF3 R 0 0 R 0 0 R 0
0 R 0 0 R 0 0 R 0 R
IF1 R 0 0 R 0 0 R 0 = Reserved
0 R 0 0 R 0 0 R 0
0 R 0 0 R 0 IF15 R 0
$FE04
$FE05
Interrupt Status Register 3 Read: $FE06 (INT3) Write: See page 131. Reset:
= Unimplemented
Figure 14-2. SIM I/O Register Summary
14.3 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The system clocks are generated from an incoming clock, BUSCLKX2, as shown in Figure 14-3.
FROM OSCILLATOR FROM OSCILLATOR
BUSCLKX4 BUSCLKX2
SIM COUNTER
/2
BUS CLOCK GENERATORS
SIM
Figure 14-3. SIM Clock Signals
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System Integration Module (SIM)
14.3.1 Bus Timing In user mode, the internal bus frequency is the oscillator frequency (BUSCLKX4) divided by four. 14.3.2 Clock Start-Up from POR When the power-on reset module generates a reset, the clocks to the CPU and peripherals are inactive and held in an inactive phase until after the 4096 BUSCLKX4 cycle POR time out has completed. The IBUS clocks start upon completion of the time out.
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14.3.3 Clocks in Stop Mode and Wait Mode Upon exit from stop mode by an interrupt or reset, the SIM allows BUSCLKX4 to clock the SIM counter. The CPU and peripheral clocks do not become active until after the stop delay time out. This time out is selectable as 4096 or 32 BUSCLKX4 cycles. See 14.7.2 Stop Mode. In wait mode, the CPU clocks are inactive. The SIM also produces two sets of clocks for other modules. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode.
14.4 Reset and System Initialization
The MCU has these reset sources: * * * * * * Power-on reset module (POR) External reset pin (RST) Computer operating properly module (COP) Low-voltage inhibit module (LVI) Illegal opcode Illegal address
All of these resets produce the vector $FFFE-FFFF ($FEFE-FEFF in monitor mode) and assert the internal reset signal (IRST). IRST causes all registers to be returned to their default values and all modules to be returned to their reset states. An internal reset clears the SIM counter (see 14.5 SIM Counter), but an external reset does not. Each of the resets sets a corresponding bit in the SIM reset status register (SRSR). See 14.8 SIM Registers.
Data Sheet 122 System Integration Module (SIM)
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System Integration Module (SIM) Reset and System Initialization
14.4.1 External Pin Reset The RST pin circuits include an internal pullup device. Pulling the asynchronous RST pin low halts all processing. The PIN bit of the SIM reset status register (SRSR) is set as long as RST is held low for at least the minimum tRL time. Figure 14-4 shows the relative timing. The RST pin function is only available if the RSTEN bit is set in the CONFIG1 register.
BUSCLKX2 RST
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ADDRESS BUS
PC
VECT H
VECT L
Figure 14-4. External Reset Timing 14.4.2 Active Resets from Internal Sources The RST pin is initially setup as a general-purpose input after a POR. Setting the RSTEN bit in the CONFIG1 register enables the pin for the reset function. This section assumes the RSTEN bit is set when describing activity on the RST pin. All internal reset sources actively pull the RST pin low for 32 BUSCLKX4 cycles to allow resetting of external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles (see Figure 14-5). An internal reset can be caused by an illegal address, illegal opcode, COP time out, LVI, or POR (see Figure 14-6). NOTE: For POR and LVI resets, the SIM cycles through 4096 BUSCLKX4 cycles during which the SIM forces the RST pin low. The internal reset signal then follows the sequence from the falling edge of RST shown in Figure 14-5. The COP reset is asynchronous to the bus clock. The active reset feature allows the part to issue a reset to peripherals and other chips within a system built around the MCU.
IRST
RST
RST PULLED LOW BY MCU 32 CYCLES 32 CYCLES
BUSCLKX4 ADDRESS BUS
VECTOR HIGH
Figure 14-5. Internal Reset Timing
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Data Sheet 123
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System Integration Module (SIM)
ILLEGAL ADDRESS RST ILLEGAL OPCODE RST COPRST POR LVI INTERNAL RESET
Figure 14-6. Sources of Internal Reset Table 14-2. Reset Recovery Timing
Reset Recovery Type POR/LVI Actual Number of Cycles 4163 (4096 + 64 + 3) 67 (64 + 3)
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All others
14.4.2.1 Power-On Reset When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate that power on has occurred. The SIM counter counts out 4096 BUSCLKX4 cycles. Sixty-four BUSCLKX4 cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur. At power on, the following events occur: * * * * * A POR pulse is generated. The internal reset signal is asserted. The SIM enables the oscillator to drive BUSCLKX4. Internal clocks to the CPU and modules are held inactive for 4096 BUSCLKX4 cycles to allow stabilization of the oscillator. The POR bit of the SIM reset status register (SRSR) is set.
See Figure 14-7. 14.4.2.2 Computer Operating Properly (COP) Reset An input to the SIM is reserved for the COP reset signal. The overflow of the COP counter causes an internal reset and sets the COP bit in the SIM reset status register (SRSR). The SIM actively pulls down the RST pin for all internal reset sources. To prevent a COP module time out, write any value to location $FFFF. Writing to location $FFFF clears the COP counter and stages 12-5 of the SIM counter. The SIM counter output, which occurs at least every (212 - 24) BUSCLKX4 cycles, drives the COP counter. The COP should be serviced as soon as possible out of reset to guarantee the maximum amount of time before the first time out. The COP module is disabled during a break interrupt with monitor mode when BDCOP bit is set in break auxiliary register (BRKAR).
Data Sheet 124 System Integration Module (SIM)
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System Integration Module (SIM) Reset and System Initialization
OSC1
PORRST 4096 CYCLES BUSCLKX4 32 CYCLES 32 CYCLES
BUSCLKX2
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RST ADDRESS BUS
(RST PIN IS A GENERAL-PURPOSE INPUT AFTER A POR) $FFFE $FFFF
Figure 14-7. POR Recovery 14.4.2.3 Illegal Opcode Reset The SIM decodes signals from the CPU to detect illegal instructions. An illegal instruction sets the ILOP bit in the SIM reset status register (SRSR) and causes a reset. If the stop enable bit, STOP, in the mask option register is 0, the SIM treats the STOP instruction as an illegal opcode and causes an illegal opcode reset. The SIM actively pulls down the RST pin for all internal reset sources. 14.4.2.4 Illegal Address Reset An opcode fetch from an unmapped address generates an illegal address reset. The SIM verifies that the CPU is fetching an opcode prior to asserting the ILAD bit in the SIM reset status register (SRSR) and resetting the MCU. A data fetch from an unmapped address does not generate a reset. The SIM actively pulls down the RST pin for all internal reset sources. See Figure 2-1. Memory Map for memory ranges. 14.4.2.5 Low-Voltage Inhibit (LVI) Reset The LVI asserts its output to the SIM when the VDD voltage falls to the LVI trip voltage VTRIPF. The LVI bit in the SIM reset status register (SRSR) is set, and the external reset pin (RST) is held low while the SIM counter counts out 4096 BUSCLKX4 cycles after VDD rises above VTRIPR. Sixty-four BUSCLKX4 cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur. The SIM actively pulls down the (RST) pin for all internal reset sources.
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Data Sheet 125
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System Integration Module (SIM)
14.5 SIM Counter
The SIM counter is used by the power-on reset module (POR) and in stop mode recovery to allow the oscillator time to stabilize before enabling the internal bus (IBUS) clocks. The SIM counter also serves as a prescaler for the computer operating properly module (COP). The SIM counter uses 12 stages for counting, followed by a 13th stage that triggers a reset of SIM counters and supplies the clock for the COP module. The SIM counter is clocked by the falling edge of BUSCLKX4. 14.5.1 SIM Counter During Power-On Reset
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The power-on reset module (POR) detects power applied to the MCU. At power-on, the POR circuit asserts the signal PORRST. Once the SIM is initialized, it enables the oscillator to drive the bus clock state machine. 14.5.2 SIM Counter During Stop Mode Recovery The SIM counter also is used for stop mode recovery. The STOP instruction clears the SIM counter. After an interrupt, break, or reset, the SIM senses the state of the short stop recovery bit, SSREC, in the configuration register 1 (CONFIG1). If the SSREC bit is a 1, then the stop recovery is reduced from the normal delay of 4096 BUSCLKX4 cycles down to 32 BUSCLKX4 cycles. This is ideal for applications using canned oscillators that do not require long start-up times from stop mode. External crystal applications should use the full stop recovery time, that is, with SSREC cleared in the configuration register 1 (CONFIG1). 14.5.3 SIM Counter and Reset States External reset has no effect on the SIM counter (see 14.7.2 Stop Mode for details.) The SIM counter is free-running after all reset states. See 14.4.2 Active Resets from Internal Sources for counter control and internal reset recovery sequences.
14.6 Exception Control
Normal sequential program execution can be changed in three different ways: 1. Interrupts a. Maskable hardware CPU interrupts b. Non-maskable software interrupt instruction (SWI) 2. Reset 3. Break interrupts 14.6.1 Interrupts An interrupt temporarily changes the sequence of program execution to respond to a particular event. Figure 14-8 flow charts the handling of system interrupts.
Data Sheet 126 System Integration Module (SIM)
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System Integration Module (SIM) Exception Control
FROM RESET
BREAK INTERRUPT? I BIT SET? NO
YES
YES
I BIT SET?
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NO
IRQ INTERRUPT? NO
YES
TIMER INTERRUPT? NO
YES
STACK CPU REGISTERS SET I BIT LOAD PC WITH INTERRUPT VECTOR
(AS MANY INTERRUPTS AS EXIST ON CHIP)
FETCH NEXT INSTRUCTION
SWI INSTRUCTION? NO
YES
RTI INSTRUCTION? NO
YES
UNSTACK CPU REGISTERS
EXECUTE INSTRUCTION
Figure 14-8. Interrupt Processing
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Data Sheet 127
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System Integration Module (SIM)
Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched interrupt is serviced (or the I bit is cleared). At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers the CPU register contents from the stack so that normal processing can resume. Figure 14-9 shows interrupt entry timing. Figure 14-10 shows interrupt recovery timing.
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MODULE INTERRUPT I BIT
ADDRESS BUS
DUMMY
SP
SP - 1
SP - 2
SP - 3
SP - 4
VECT H
VECT L
START ADDR
DATA BUS
DUMMY
PC - 1[7:0] PC - 1[15:8]
X
A
CCR
V DATA H
V DATA L
OPCODE
R/W
Figure 14-9. Interrupt Entry
MODULE INTERRUPT I BIT
ADDRESS BUS
SP - 4
SP - 3
SP - 2
SP - 1
SP
PC
PC + 1
DATA BUS
CCR
A
X
PC - 1[7:0] PC - 1[15:8] OPCODE
OPERAND
R/W
Figure 14-10. Interrupt Recovery 14.6.1.1 Hardware Interrupts A hardware interrupt does not stop the current instruction. Processing of a hardware interrupt begins after completion of the current instruction. When the current instruction is complete, the SIM checks all pending hardware interrupts. If interrupts are not masked (I bit clear in the condition code register), and if the corresponding interrupt enable bit is set, the SIM proceeds with interrupt processing; otherwise, the next instruction is fetched and executed.
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System Integration Module (SIM) Exception Control
If more than one interrupt is pending at the end of an instruction execution, the highest priority interrupt is serviced first. Figure 14-11 demonstrates what happens when two interrupts are pending. If an interrupt is pending upon exit from the original interrupt service routine, the pending interrupt is serviced before the LDA instruction is executed.
CLI LDA #$FF BACKGROUND ROUTINE
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INT1
PSHH INT1 INTERRUPT SERVICE ROUTINE PULH RTI
INT2
PSHH INT2 INTERRUPT SERVICE ROUTINE PULH RTI
Figure 14-11. Interrupt Recognition Example The LDA opcode is prefetched by both the INT1 and INT2 return-from-interrupt (RTI) instructions. However, in the case of the INT1 RTI prefetch, this is a redundant operation. NOTE: To maintain compatibility with the M6805 Family, the H register is not pushed on the stack during interrupt entry. If the interrupt service routine modifies the H register or uses the indexed addressing mode, software should save the H register and then restore it prior to exiting the routine.
14.6.1.2 SWI Instruction The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the interrupt mask (I bit) in the condition code register. NOTE: A software interrupt pushes PC onto the stack. A software interrupt does not push PC - 1, as a hardware interrupt does.
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Data Sheet 129
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System Integration Module (SIM)
14.6.2 Interrupt Status Registers The flags in the interrupt status registers identify maskable interrupt sources. Table 14-3 summarizes the interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be useful for debugging. Table 14-3. Interrupt Sources
Priority Highest Reset SWI instruction IRQ pin Timer channel 0 interrupt Timer channel 1 interrupt Timer overflow interrupt Keyboard interrupt Lowest ADC conversion complete interrupt Source Flag -- -- IRQF CH0F CH1F TOF KEYF COCO Mask(1) -- -- IMASK CH0IE CH1IE TOIE IMASKK AIEN INT Register Flag -- -- IF1 IF3 IF4 IF5 IF14 IF15 Vector Address $FFFE-$FFFF $FFFC-$FFFD $FFFA-$FFFB $FFF6-$FFF7 $FFF4-$FFF5 $FFF2-$FFF3 $FFE0-$FFE1 $FFDE-$FFDF
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1. The I bit in the condition code register is a global mask for all interrupt sources except the SWI instruction.
14.6.2.1 Interrupt Status Register 1
Address: $FE04 Bit 7 Read: Write: Reset: 0 R 0 R 6 IF5 R 0 = Reserved 5 IF4 R 0 4 IF3 R 0 3 0 R 0 2 IF1 R 0 1 0 R 0 Bit 0 0 R 0
Figure 14-12. Interrupt Status Register 1 (INT1) IF1 and IF3-IF5 -- Interrupt Flags These flags indicate the presence of interrupt requests from the sources shown in Table 14-3. 1 = Interrupt request present 0 = No interrupt request present Bit 0, 1, 3, and 7 -- Always read 0
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System Integration Module (SIM) Exception Control
14.6.2.2 Interrupt Status Register 2
Address: $FE05 Bit 7 Read: Write: Reset: IF14 R 0 R 6 0 R 0 = Reserved 5 0 R 0 4 0 R 0 3 0 R 0 2 0 R 0 1 0 R 0 Bit 0 0 R 0
Figure 14-13. Interrupt Status Register 2 (INT2)
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IF14 -- Interrupt Flags This flag indicates the presence of interrupt requests from the sources shown in Table 14-3. 1 = Interrupt request present 0 = No interrupt request present Bit 0-6 -- Always read 0 14.6.2.3 Interrupt Status Register 3
Address: $FE06 Bit 7 Read: Write: Reset: 0 R 0 R 6 0 R 0 = Reserved 5 0 R 0 4 0 R 0 3 0 R 0 2 0 R 0 1 0 R 0 Bit 0 IF15 R 0
Figure 14-14. Interrupt Status Register 3 (INT3) IF15 -- Interrupt Flags These flags indicate the presence of interrupt requests from the sources shown in Table 14-3. 1 = Interrupt request present 0 = No interrupt request present Bit 1-7 -- Always read 0 14.6.3 Reset All reset sources always have equal and highest priority and cannot be arbitrated. 14.6.4 Break Interrupts The break module can stop normal program flow at a software programmable break point by asserting its break interrupt output. (See Section 16. Development Support.) The SIM puts the CPU into the break state by forcing it to the SWI vector
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System Integration Module (SIM)
location. Refer to the break interrupt subsection of each module to see how each module is affected by the break state. 14.6.5 Status Flag Protection in Break Mode The SIM controls whether status flags contained in other modules can be cleared during break mode. The user can select whether flags are protected from being cleared by properly initializing the break clear flag enable bit (BCFE) in the break flag control register (BFCR). Protecting flags in break mode ensures that set flags will not be cleared while in break mode. This protection allows registers to be freely read and written during break mode without losing status flag information. Setting the BCFE bit enables the clearing mechanisms. Once cleared in break mode, a flag remains cleared even when break mode is exited. Status flags with a two-step clearing mechanism -- for example, a read of one register followed by the read or write of another -- are protected, even when the first step is accomplished prior to entering break mode. Upon leaving break mode, execution of the second step will clear the flag as normal.
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14.7 Low-Power Modes
Executing the WAIT or STOP instruction puts the MCU in a low power-consumption mode for standby situations. The SIM holds the CPU in a non-clocked state. The operation of each of these modes is described below. Both STOP and WAIT clear the interrupt mask (I) in the condition code register, allowing interrupts to occur. 14.7.1 Wait Mode In wait mode, the CPU clocks are inactive while the peripheral clocks continue to run. Figure 14-15 shows the timing for wait mode entry.
ADDRESS BUS
WAIT ADDR
WAIT ADDR + 1
SAME
SAME
DATA BUS
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction.
Figure 14-15. Wait Mode Entry Timing
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System Integration Module (SIM) Low-Power Modes
A module that is active during wait mode can wake up the CPU with an interrupt if the interrupt is enabled. Stacking for the interrupt begins one cycle after the WAIT instruction during which the interrupt occurred. In wait mode, the CPU clocks are inactive. Refer to the wait mode subsection of each module to see if the module is active or inactive in wait mode. Some modules can be programmed to be active in wait mode. Wait mode can also be exited by a reset (or break in emulation mode). A break interrupt during wait mode sets the SIM break stop/wait bit, SBSW, in the break status register (BSR). If the COP disable bit, COPD, in the configuration register is 0, then the computer operating properly module (COP) is enabled and remains active in wait mode.
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Figure 14-16 and Figure 14-17 show the timing for wait recovery.
ADDRESS BUS
$6E0B
$6E0C
$00FF
$00FE
$00FD
$00FC
DATA BUS
$A6
$A6
$A6
$01
$0B
$6E
EXITSTOPWAIT NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt
Figure 14-16. Wait Recovery from Interrupt
32 CYCLES ADDRESS BUS $6E0B 32 CYCLES RSTVCT H RSTVCT L
DATA BUS RST(1)
$A6
$A6
$A6
BUSCLKX4 1. RST is only available if the RSTEN bit in the CONFIG1 register is set.
Figure 14-17. Wait Recovery from Internal Reset 14.7.2 Stop Mode In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery time has elapsed. Reset or break also causes an exit from stop mode.
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System Integration Module (SIM)
The SIM disables the oscillator signals (BUSCLKX2 and BUSCLKX4) in stop mode, stopping the CPU and peripherals. Stop recovery time is selectable using the SSREC bit in the configuration register 1 (CONFIG1). If SSREC is set, stop recovery is reduced from the normal delay of 4096 BUSCLKX4 cycles down to 32. This is ideal for the internal oscillator, RC oscillator, and external oscillator options which do not require long start-up times from stop mode. NOTE: External crystal applications should use the full stop recovery time by clearing the SSREC bit. The SIM counter is held in reset from the execution of the STOP instruction until the beginning of stop recovery. It is then used to time the recovery period. Figure 14-18 shows stop mode entry timing and Figure 14-19 shows the stop mode recovery time from interrupt or break NOTE: To minimize stop current, all pins configured as inputs should be driven to a logic 1 or logic 0.
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CPUSTOP
ADDRESS BUS
STOP ADDR
STOP ADDR + 1
SAME
SAME
DATA BUS
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W NOTE: Previous data can be operand data or the STOP opcode, depending on the last instruction.
Figure 14-18. Stop Mode Entry Timing
STOP RECOVERY PERIOD BUSCLKX4
INTERRUPT
ADDRESS BUS
STOP +1
STOP + 2
STOP + 2
SP
SP - 1
SP - 2
SP - 3
Figure 14-19. Stop Mode Recovery from Interrupt
Data Sheet 134 System Integration Module (SIM)
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System Integration Module (SIM) SIM Registers
14.8 SIM Registers
The SIM has three memory mapped registers. Table 14-4 shows the mapping of these registers. Table 14-4. SIM Registers
Address $FE00 $FE01 $FE03 Register BSR SRSR BFCR Access Mode User User User
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14.8.1 SIM Reset Status Register This register contains seven flags that show the source of the last reset. Clear the SIM reset status register by reading it. A power-on reset sets the POR bit and clears all other bits in the register.
Address: $FE01 Bit 7 Read: Write: POR: 1 0 = Unimplemented 0 0 0 0 0 0 POR 6 PIN 5 COP 4 ILOP 3 ILAD 2 MODRST 1 LVI Bit 0 0
Figure 14-20. SIM Reset Status Register (SRSR) POR -- Power-On Reset Bit 1 = Last reset caused by POR circuit 0 = Read of SRSR PIN -- External Reset Bit 1 = Last reset caused by external reset pin (RST) 0 = POR or read of SRSR COP -- Computer Operating Properly Reset Bit 1 = Last reset caused by COP counter 0 = POR or read of SRSR ILOP -- Illegal Opcode Reset Bit 1 = Last reset caused by an illegal opcode 0 = POR or read of SRSR ILAD -- Illegal Address Reset Bit (illegal attempt to fetch an opcode from an unimplemented address) 1 = Last reset caused by an opcode fetch from an illegal address 0 = POR or read of SRSR
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Data Sheet 135
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System Integration Module (SIM)
MODRST -- Monitor Mode Entry Module Reset Bit 1 = Last reset caused by monitor mode entry when vector locations $FFFE and $FFFF are $FF after POR while IRQ = VDD 0 = POR or read of SRSR LVI -- Low Voltage Inhibit Reset bit 1 = Last reset caused by LVI circuit 0 = POR or read of SRSR 14.8.2 Break Flag Control Register The break control register (BFCR) contains a bit that enables software to clear status bits while the MCU is in a break state.
Address: $FE03 Bit 7 Read: Write: Reset: BCFE 0 R = Reserved 6 R 5 R 4 R 3 R 2 R 1 R Bit 0 R
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Figure 14-21. Break Flag Control Register (BFCR) BCFE -- Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break
Data Sheet 136 System Integration Module (SIM)
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Data Sheet -- MC68HC908QF4
Section 15. Timer Interface Module (TIM)
15.1 Introduction
This section describes the timer interface module (TIM). The TIM is a two-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. Figure 15-2 is a block diagram of the TIM.
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15.2 Features
Features of the TIM include the following: * Two input capture/output compare channels - Rising-edge, falling-edge, or any-edge input capture trigger - Set, clear, or toggle output compare action Buffered and unbuffered pulse width modulation (PWM) signal generation Programmable TIM clock input - 7-frequency internal bus clock prescaler selection - External TIM clock input Free-running or modulo up-count operation Toggle any channel pin on overflow TIM counter stop and reset bits
* *
* * *
15.3 Pin Name Conventions
The TIM shares two input/output (I/O) pins with two port A I/O pins. The full names of the TIM I/O pins are listed in Table 15-1. The generic pin name appear in the text that follows. Table 15-1. Pin Name Conventions
TIM Generic Pin Names: Full TIM Pin Names: TCH0 PTA0/TCH0 TCH1 PTA1/TCH1 TCLK PTA2/TCLK
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Data Sheet 137
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Timer Interface Module (TIM)
PTA0/AD0/TCH0/KBI0 PTA1/AD1/TCH1/KBI1 DDRA PTA PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 M68HC08 CPU PTB0 PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 CLOCK GENERATOR (OSCILLATOR)
SYSTEM INTEGRATION MODULE SINGLE INTERRUPT MODULE BREAK MODULE POWER-ON RESET MODULE KEYBOARD INTERRUPT MODULE 16-BIT TIMER MODULE COP MODULE VCC MODE PLLEN DATA BS OP1 GND REXT XTAL1 XTAL0 UPCLK PFD
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8-BIT ADC
DDRB
PTB
MC68HC908QF4 4096 BYTES USER FLASH
128 BYTES RAM
MONITOR ROM
UHF TRANSMITTER
VDD POWER SUPPLY VSS
RST, IRQ: Pins have internal (about 30K Ohms) pull up PTA[0:5]: High current sink and source capability PTA[0:5]: Pins have programmable keyboard interrupt and pull up
Figure 15-1. Block Diagram Highlighting TIM Block and Pins
Data Sheet 138 Timer Interface Module (TIM)
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Timer Interface Module (TIM) Functional Description
15.4 Functional Description
Figure 15-2 shows the structure of the TIM. The central component of the TIM is the 16-bit TIM counter that can operate as a free-running counter or a modulo up-counter. The TIM counter provides the timing reference for the input capture and output compare functions. The TIM counter modulo registers, TMODH:TMODL, control the modulo value of the TIM counter. Software can read the TIM counter value at any time without affecting the counting sequence. The two TIM channels are programmable independently as input capture or output compare channels.
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PTA2/IRQ/KBI2/TCLK PRESCALER SELECT INTERNAL BUS CLOCK TSTOP TRST 16-BIT COUNTER 16-BIT COMPARATOR TMODH:TMODL TOV0 CHANNEL 0 16-BIT COMPARATOR TCH0H:TCH0L 16-BIT LATCH MS0A MS0B TOV1 INTERNAL BUS CHANNEL 1 16-BIT COMPARATOR TCH1H:TCH1L 16-BIT LATCH MS1A CH1IE CH1F INTERRUPT LOGIC ELS1B ELS1A CH1MAX PORT LOGIC TCH1 CH0IE CH0F INTERRUPT LOGIC ELS0B ELS0A CH0MAX PORT LOGIC TCH0 PRESCALER
PS2
PS1
PS0
TOF TOIE
INTERRUPT LOGIC
Figure 15-2. TIM Block Diagram
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Data Sheet 139
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Timer Interface Module (TIM)
Addr. $0020
Register Name TIM Status and Control Register (TSC) See page 147. TIM Counter Register High (TCNTH) See page 149. TIM Counter Register Low (TCNTL) See page 149. TIM Counter Modulo Register High (TMODH) See page 149. TIM Counter Modulo Register Low (TMODL) See page 149. TIM Channel 0 Status and Control Register (TSC0) See page 150. TIM Channel 0 Register High (TCH0H) See page 153. TIM Channel 0 Register Low (TCH0L) See page 153. TIM Channel 1 Status and Control Register (TSC1) See page 150. TIM Channel 1 Register High (TCH1H) See page 153. TIM Channel 1 Register Low (TCH1L) See page 153. Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset:
Bit 7 TOF 0 0 Bit 15 0 Bit 7 0 Bit 15 1 Bit 7 1 CH0F 0 0 Bit 15
6 TOIE 0 Bit 14 0 Bit 6 0 Bit 14 1 Bit 6 1 CH0IE 0 Bit 14
5 TSTOP 1 Bit 13 0 Bit 5 0 Bit 13 1 Bit 5 1 MS0B 0 Bit 13
4 0 TRST 0 Bit 12 0 Bit 4 0 Bit 12 1 Bit 4 1 MS0A 0 Bit 12
3 0 0 Bit 11 0 Bit 3 0 Bit 11 1 Bit 3 1 ELS0B 0 Bit 11
2 PS2 0 Bit 10 0 Bit 2 0 Bit 10 1 Bit 2 1 ELS0A 0 Bit 10
1 PS1 0 Bit 9 0 Bit 1 0 Bit 9 1 Bit 1 1 TOV0 0 Bit 9
Bit 0 PS0 0 Bit 8 0 Bit 0 0 Bit 8 1 Bit 0 1 CH0MAX 0 Bit 8
$0021
$0022
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$0023
$0024
$0025
$0026
Indeterminate after reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$0027
Indeterminate after reset CH1F 0 0 Bit 15 CH1IE 0 Bit 14 0 0 Bit 13 MS1A 0 Bit 12 ELS1B 0 Bit 11 ELS1A 0 Bit 10 TOV1 0 Bit 9 CH1MAX 0 Bit 8
$0028
$0029
Indeterminate after reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$002A
Indeterminate after reset = Unimplemented
Figure 15-3. TIM I/O Register Summary
Data Sheet 140 Timer Interface Module (TIM)
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Timer Interface Module (TIM) Functional Description
15.4.1 TIM Counter Prescaler The TIM clock source is one of the seven prescaler outputs or the TIM clock pin, TCLK. The prescaler generates seven clock rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIM status and control register (TSC) select the TIM clock source. 15.4.2 Input Capture With the input capture function, the TIM can capture the time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the TIM latches the contents of the TIM counter into the TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input captures can generate TIM central processor unit (CPU) interrupt requests. 15.4.3 Output Compare With the output compare function, the TIM can generate a periodic pulse with a programmable polarity, duration, and frequency. When the counter reaches the value in the registers of an output compare channel, the TIM can set, clear, or toggle the channel pin. Output compares can generate TIM CPU interrupt requests. 15.4.3.1 Unbuffered Output Compare Any output compare channel can generate unbuffered output compare pulses as described in 15.4.3 Output Compare. The pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the TIM channel registers. An unsynchronized write to the TIM channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. Also, using a TIM overflow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. The TIM may pass the new value before it is written. Use the following methods to synchronize unbuffered changes in the output compare value on channel x: * When changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current output compare pulse. The interrupt routine has until the end of the counter overflow period to write the new value. When changing to a larger output compare value, enable TIM overflow interrupts and write the new value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current counter overflow
Data Sheet Timer Interface Module (TIM) 141
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*
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Timer Interface Module (TIM)
period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. 15.4.3.2 Buffered Output Compare Channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the TCH0 pin. The TIM channel registers of the linked pair alternately control the output. Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1. The output compare value in the TIM channel 0 registers initially controls the output on the TCH0 pin. Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the output after the TIM overflows. At each subsequent overflow, the TIM channel registers (0 or 1) that control the output are the ones written to last. TSC0 controls and monitors the buffered output compare function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available as a general-purpose I/O pin. NOTE: In buffered output compare operation, do not write new output compare values to the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered output compares.
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15.4.4 Pulse Width Modulation (PWM) By using the toggle-on-overflow feature with an output compare channel, the TIM can generate a PWM signal. The value in the TIM counter modulo registers determines the period of the PWM signal. The channel pin toggles when the counter reaches the value in the TIM counter modulo registers. The time between overflows is the period of the PWM signal. As Figure 15-4 shows, the output compare value in the TIM channel registers determines the pulse width of the PWM signal. The time between overflow and output compare is the pulse width. Program the TIM to clear the channel pin on output compare if the state of the PWM pulse is logic 1 (ELSxA = 0). Program the TIM to set the pin if the state of the PWM pulse is logic 0 (ELSxA = 1). The value in the TIM counter modulo registers and the selected prescaler output determines the frequency of the PWM output. The frequency of an 8-bit PWM signal is variable in 256 increments. Writing $00FF (255) to the TIM counter modulo registers produces a PWM period of 256 times the internal bus clock period if the prescaler select value is 000. See 15.9.1 TIM Status and Control Register. The value in the TIM channel registers determines the pulse width of the PWM output. The pulse width of an 8-bit PWM signal is variable in 256 increments. Writing $0080 (128) to the TIM channel registers produces a duty cycle of 128/256 or 50%.
Data Sheet 142 Timer Interface Module (TIM) MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Timer Interface Module (TIM) Functional Description
OVERFLOW PERIOD POLARITY = 1 (ELSxA = 0) TCHx PULSE WIDTH POLARITY = 0 (ELSxA = 1) TCHx
OVERFLOW
OVERFLOW
OUTPUT COMPARE
OUTPUT COMPARE
OUTPUT COMPARE
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Figure 15-4. PWM Period and Pulse Width 15.4.4.1 Unbuffered PWM Signal Generation Any output compare channel can generate unbuffered PWM pulses as described in 15.4.4 Pulse Width Modulation (PWM). The pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the TIM channel registers. An unsynchronized write to the TIM channel registers to change a pulse width value could cause incorrect operation for up to two PWM periods. For example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that PWM period. Also, using a TIM overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. The TIM may pass the new value before it is written. Use the following methods to synchronize unbuffered changes in the PWM pulse width on channel x: * When changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. The output compare interrupt occurs at the end of the current pulse. The interrupt routine has until the end of the PWM period to write the new value. When changing to a longer pulse width, enable TIM overflow interrupts and write the new value in the TIM overflow interrupt routine. The TIM overflow interrupt occurs at the end of the current PWM period. Writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same PWM period.
*
NOTE:
In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. Toggling on output compare also can cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value.
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Data Sheet 143
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Timer Interface Module (TIM)
15.4.4.2 Buffered PWM Signal Generation Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the TCH0 pin. The TIM channel registers of the linked pair alternately control the pulse width of the output. Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1. The TIM channel 0 registers initially control the pulse width on the TCH0 pin. Writing to the TIM channel 1 registers enables the TIM channel 1 registers to synchronously control the pulse width at the beginning of the next PWM period. At each subsequent overflow, the TIM channel registers (0 or 1) that control the pulse width are the ones written to last. TSC0 controls and monitors the buffered PWM function, and TIM channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1, is available as a general-purpose I/O pin. NOTE: In buffered PWM signal generation, do not write new pulse width values to the currently active channel registers. User software should track the currently active channel to prevent writing a new value to the active channel. Writing to the active channel registers is the same as generating unbuffered PWM signals.
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15.4.4.3 PWM Initialization To ensure correct operation when generating unbuffered or buffered PWM signals, use the following initialization procedure: 1. In the TIM status and control register (TSC): a. Stop the TIM counter by setting the TIM stop bit, TSTOP. b. Reset the TIM counter and prescaler by setting the TIM reset bit, TRST. 2. In the TIM counter modulo registers (TMODH:TMODL), write the value for the required PWM period. 3. In the TIM channel x registers (TCHxH:TCHxL), write the value for the required pulse width. 4. In TIM channel x status and control register (TSCx): a. Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare or PWM signals) to the mode select bits, MSxB:MSxA. See Table 15-3. b. Write 1 to the toggle-on-overflow bit, TOVx. c. Write 1:0 (polarity 1 -- to clear output on compare) or 1:1 (polarity 0 -- to set output on compare) to the edge/level select bits, ELSxB:ELSxA. The output action on compare must force the output to the complement of the pulse width level. See Table 15-3. NOTE: In PWM signal generation, do not program the PWM channel to toggle on output compare. Toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error
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Data Sheet 144
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Timer Interface Module (TIM) Interrupts
or noise. Toggling on output compare can also cause incorrect PWM signal generation when changing the PWM pulse width to a new, much larger value. 5. In the TIM status control register (TSC), clear the TIM stop bit, TSTOP. Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM channel 0 registers (TCH0H:TCH0L) initially control the buffered PWM output. TIM status control register 0 (TSCR0) controls and monitors the PWM signal from the linked channels. MS0B takes priority over MS0A. Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM overflows. Subsequent output compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle output. Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty cycle output. See 15.9.4 TIM Channel Status and Control Registers.
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15.5 Interrupts
The following TIM sources can generate interrupt requests: * TIM overflow flag (TOF) -- The TOF bit is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE, enables TIM overflow CPU interrupt requests. TOF and TOIE are in the TIM status and control register. TIM channel flags (CH1F:CH0F) -- The CHxF bit is set when an input capture or output compare occurs on channel x. Channel x TIM CPU interrupt requests are controlled by the channel x interrupt enable bit, CHxIE. Channel x TIM CPU interrupt requests are enabled when CHxIE =1. CHxF and CHxIE are in the TIM channel x status and control register.
*
15.6 Wait Mode
The WAIT instruction puts the MCU in low power-consumption standby mode. The TIM remains active after the execution of a WAIT instruction. In wait mode the TIM registers are not accessible by the CPU. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait mode. If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before executing the WAIT instruction.
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Data Sheet 145
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Timer Interface Module (TIM)
15.7 TIM During Break Interrupts
A break interrupt stops the TIM counter. The system integration module (SIM) controls whether status bits in other modules can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. See 16.2.2.5 Break Flag Control Register. To allow software to clear status bits during a break interrupt, write a 1 to the BCFE bit. If a status bit is cleared during the break state, it remains cleared when the MCU exits the break state.
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To protect status bits during the break state, write a 0 to the BCFE bit. With BCFE at 0 (its default state), software can read and write I/O registers during the break state without affecting status bits. Some status bits have a two-step read/write clearing procedure. If software does the first step on such a bit before the break, the bit cannot change during the break state as long as BCFE is at 0. After the break, doing the second step clears the status bit.
15.8 Input/Output Signals
Port A shares three of its pins with the TIM. Two TIM channel I/O pins are PTA0/TCH0 and PTA1/TCH1 and an alternate clock source is PTA2/TCLK. 15.8.1 TIM Clock Pin (PTA2/TCLK)
PTA2/TCLK is an external clock input that can be the clock source for the TIM
counter instead of the prescaled internal bus clock. Select the PTA2/TCLK input by writing 1s to the three prescaler select bits, PS[2-0]. (See 15.9.1 TIM Status and Control Register.) When the PTA2/TCLK pin is the TIM clock input, it is an input regardless of port pin initialization. 15.8.2 TIM Channel I/O Pins (PTA0/TCH0 and PTA1/TCH1) Each channel I/O pin is programmable independently as an input capture pin or an output compare pin. PTA0/TCH0 can be configured as a buffered output compare or buffered PWM pin.
Data Sheet 146 Timer Interface Module (TIM)
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Timer Interface Module (TIM) Input/Output Registers
15.9 Input/Output Registers
The following I/O registers control and monitor operation of the TIM: * * * * * TIM status and control register (TSC) TIM counter registers (TCNTH:TCNTL) TIM counter modulo registers (TMODH:TMODL) TIM channel status and control registers (TSC0 and TSC1) TIM channel registers (TCH0H:TCH0L and TCH1H:TCH1L)
15.9.1 TIM Status and Control Register
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The TIM status and control register (TSC) does the following: * * * * * Enables TIM overflow interrupts Flags TIM overflows Stops the TIM counter Resets the TIM counter Prescales the TIM counter clock
Address: $0020 Bit 7 Read: Write: Reset: TOF 0 0 6 TOIE 0 = Unimplemented 5 TSTOP 1 4 0 TRST 0 0 3 0 2 PS2 0 1 PS1 0 Bit 0 PS0 0
Figure 15-5. TIM Status and Control Register (TSC) TOF -- TIM Overflow Flag Bit This read/write flag is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers. Clear TOF by reading the TIM status and control register when TOF is set and then writing a 0 to TOF. If another TIM overflow occurs before the clearing sequence is complete, then writing 0 to TOF has no effect. Therefore, a TOF interrupt request cannot be lost due to inadvertent clearing of TOF. Reset clears the TOF bit. Writing a 1 to TOF has no effect. 1 = TIM counter has reached modulo value 0 = TIM counter has not reached modulo value TOIE -- TIM Overflow Interrupt Enable Bit This read/write bit enables TIM overflow interrupts when the TOF bit becomes set. Reset clears the TOIE bit. 1 = TIM overflow interrupts enabled 0 = TIM overflow interrupts disabled
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Data Sheet 147
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Timer Interface Module (TIM)
TSTOP -- TIM Stop Bit This read/write bit stops the TIM counter. Counting resumes when TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIM counter until software clears the TSTOP bit. 1 = TIM counter stopped 0 = TIM counter active NOTE: Do not set the TSTOP bit before entering wait mode if the TIM is required to exit wait mode. TRST -- TIM Reset Bit Setting this write-only bit resets the TIM counter and the TIM prescaler. Setting TRST has no effect on any other registers. Counting resumes from $0000. TRST is cleared automatically after the TIM counter is reset and always reads as a 0. Reset clears the TRST bit. 1 = Prescaler and TIM counter cleared 0 = No effect NOTE: Setting the TSTOP and TRST bits simultaneously stops the TIM counter at a value of $0000. PS[2:0] -- Prescaler Select Bits These read/write bits select either the PTA2/TCLK pin or one of the seven prescaler outputs as the input to the TIM counter as Table 15-2 shows. Reset clears the PS[2:0] bits. Table 15-2. Prescaler Selection
PS2 0 0 0 0 1 1 1 1 PS1 0 0 1 1 0 0 1 1 PS0 0 1 0 1 0 1 0 1 TIM Clock Source Internal bus clock / 1 Internal bus clock / 2 Internal bus clock / 4 Internal bus clock / 8 Internal bus clock / 16 Internal bus clock / 32 Internal bus clock / 64 PTA2/TCLK
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Data Sheet 148
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Timer Interface Module (TIM) Input/Output Registers
15.9.2 TIM Counter Registers The two read-only TIM counter registers contain the high and low bytes of the value in the TIM counter. Reading the high byte (TCNTH) latches the contents of the low byte (TCNTL) into a buffer. Subsequent reads of TCNTH do not affect the latched TCNTL value until TCNTL is read. Reset clears the TIM counter registers. Setting the TIM reset bit (TRST) also clears the TIM counter registers. NOTE: If you read TCNTH during a break interrupt, be sure to unlatch TCNTL by reading TCNTL before exiting the break interrupt. Otherwise, TCNTL retains the value latched during the break.
Address: $0021 Bit 7 Read: Write: Reset: 0 Bit 7 Read: Write: Reset: 0 0 = Unimplemented 0 0 0 0 0 0 Bit 7 0 TCNTL 6 Bit 6 5 Bit 5 4 Bit 4 3 Bit 3 2 Bit 2 1 Bit 1 Bit 0 Bit 0 0 0 0 0 0 0 Address: $0022 Bit 15 TCNTH 6 Bit 14 5 Bit 13 4 Bit 12 3 Bit 11 2 Bit 10 1 Bit 9 Bit 0 Bit 8
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Figure 15-6. TIM Counter Registers (TCNTH:TCNTL) 15.9.3 TIM Counter Modulo Registers The read/write TIM modulo registers contain the modulo value for the TIM counter. When the TIM counter reaches the modulo value, the overflow flag (TOF) becomes set, and the TIM counter resumes counting from $0000 at the next timer clock. Writing to the high byte (TMODH) inhibits the TOF bit and overflow interrupts until the low byte (TMODL) is written. Reset sets the TIM counter modulo registers.
Address: $0023 Bit 7 Read: Write: Reset: Bit 15 1 Bit 7 Read: Write: Reset: Bit 7 1 TMODH 6 Bit 14 1 TMODL 6 Bit 6 1 5 Bit 5 1 4 Bit 4 1 3 Bit 3 1 2 Bit 2 1 1 Bit 1 1 Bit 0 Bit 0 1 5 Bit 13 1 4 Bit 12 1 3 Bit 11 1 2 Bit 10 1 1 Bit 9 1 Bit 0 Bit 8 1
Address: $0024
Figure 15-7. TIM Counter Modulo Registers (TMODH:TMODL) NOTE: Reset the TIM counter before writing to the TIM counter modulo registers.
Data Sheet Timer Interface Module (TIM) 149
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Timer Interface Module (TIM)
15.9.4 TIM Channel Status and Control Registers Each of the TIM channel status and control registers does the following: * * * * * * * * Flags input captures and output compares Enables input capture and output compare interrupts Selects input capture, output compare, or PWM operation Selects high, low, or toggling output on output compare Selects rising edge, falling edge, or any edge as the active input capture trigger Selects output toggling on TIM overflow Selects 0% and 100% PWM duty cycle Selects buffered or unbuffered output compare/PWM operation
TSC0 6 CH0IE 0 TSC1 6 CH1IE 0 = Unimplemented 5 0 0 4 MS1A 0 3 ELS1B 0 2 ELS1A 0 1 TOV1 0 Bit 0 CH1MAX 0 5 MS0B 0 4 MS0A 0 3 ELS0B 0 2 ELS0A 0 1 TOV0 0 Bit 0 CH0MAX 0
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Address: $0025 Bit 7 Read: Write: Reset: CH0F 0 0
Address: $0028 Bit 7 Read: Write: Reset: CH1F 0 0
Figure 15-8. TIM Channel Status and Control Registers (TSC0:TSC1) CHxF -- Channel x Flag Bit When channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the TIM counter registers matches the value in the TIM channel x registers. Clear CHxF by reading the TIM channel x status and control register with CHxF set and then writing a 0 to CHxF. If another interrupt request occurs before the clearing sequence is complete, then writing a 0 to CHxF has no effect. Therefore, an interrupt request cannot be lost due to inadvertent clearing of CHxF. Reset clears the CHxF bit. Writing a 1 to CHxF has no effect. 1 = Input capture or output compare on channel x 0 = No input capture or output compare on channel x
Data Sheet 150 Timer Interface Module (TIM)
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Timer Interface Module (TIM) Input/Output Registers
CHxIE -- Channel x Interrupt Enable Bit This read/write bit enables TIM CPU interrupt service requests on channel x. Reset clears the CHxIE bit. 1 = Channel x CPU interrupt requests enabled 0 = Channel x CPU interrupt requests disabled MSxB -- Mode Select Bit B This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIM channel 0 status and control register. Setting MS0B disables the channel 1 status and control register and reverts TCH1 to general-purpose I/O.
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Reset clears the MSxB bit. 1 = Buffered output compare/PWM operation enabled 0 = Buffered output compare/PWM operation disabled MSxA -- Mode Select Bit A When ELSxB:A 00, this read/write bit selects either input capture operation or unbuffered output compare/PWM operation. See Table 15-3. 1 = Unbuffered output compare/PWM operation 0 = Input capture operation When ELSxB:A = 00, this read/write bit selects the initial output level of the TCHx pin (see Table 15-3). Reset clears the MSxA bit. 1 = Initial output level low 0 = Initial output level high NOTE: Before changing a channel function by writing to the MSxB or MSxA bit, set the TSTOP and TRST bits in the TIM status and control register (TSC). Table 15-3. Mode, Edge, and Level Selection
MSxB X X 0 0 0 0 0 0 0 1 1 1 MC68HC908QF4 -- Rev. 1.0 MOTOROLA Timer Interface Module (TIM) MSxA 0 1 0 0 0 1 1 1 1 X X X ELSxB 0 0 0 1 1 0 0 1 1 0 1 1 ELSxA 0 Output preset 0 1 0 1 0 1 0 1 1 0 1 Buffered output compare or buffered PWM Output compare or PWM Input capture Mode Configuration Pin under port control; initial output level high Pin under port control; initial output level low Capture on rising edge only Capture on falling edge only Capture on rising or falling edge Software compare only Toggle output on compare Clear output on compare Set output on compare Toggle output on compare Clear output on compare Set output on compare Data Sheet 151
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Timer Interface Module (TIM)
ELSxB and ELSxA -- Edge/Level Select Bits When channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x. When channel x is an output compare channel, ELSxB and ELSxA control the channel x output behavior when an output compare occurs. When ELSxB and ELSxA are both clear, channel x is not connected to an I/O port, and pin TCHx is available as a general-purpose I/O pin. Table 15-3 shows how ELSxB and ELSxA work. Reset clears the ELSxB and ELSxA bits. NOTE: After initially enabling a TIM channel register for input capture operation and selecting the edge sensitivity, clear CHxF to ignore any erroneous edge detection flags. TOVx -- Toggle-On-Overflow Bit When channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the TIM counter overflows. When channel x is an input capture channel, TOVx has no effect. Reset clears the TOVx bit. 1 = Channel x pin toggles on TIM counter overflow. 0 = Channel x pin does not toggle on TIM counter overflow. NOTE: When TOVx is set, a TIM counter overflow takes precedence over a channel x output compare if both occur at the same time. CHxMAX -- Channel x Maximum Duty Cycle Bit When the TOVx bit is a 1, setting the CHxMAX bit forces the duty cycle of buffered and unbuffered PWM signals to 100%. As Figure 15-9 shows, the CHxMAX bit takes effect in the cycle after it is set or cleared. The output stays at the 100% duty cycle level until the cycle after CHxMAX is cleared.
OVERFLOW PERIOD OVERFLOW OVERFLOW OVERFLOW OVERFLOW
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TCHx
OUTPUT COMPARE CHxMAX
OUTPUT COMPARE
OUTPUT COMPARE
OUTPUT COMPARE
Figure 15-9. CHxMAX Latency
Data Sheet 152 Timer Interface Module (TIM)
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Timer Interface Module (TIM) Input/Output Registers
15.9.5 TIM Channel Registers These read/write registers contain the captured TIM counter value of the input capture function or the output compare value of the output compare function. The state of the TIM channel registers after reset is unknown. In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registers (TCHxH) inhibits input captures until the low byte (TCHxL) is read. In output compare mode (MSxB:MSxA 0:0), writing to the high byte of the TIM channel x registers (TCHxH) inhibits output compares until the low byte (TCHxL) is written.
Address: $0026 Bit 7 Read: Write: Reset: Address: $0027 Bit 7 Read: Write: Reset: Bit 7 TCH0L 6 Bit 6 5 Bit 5 4 Bit 4 3 Bit 3 2 Bit 2 1 Bit 1 Bit 0 Bit 0 Bit 15 TCH0H 6 Bit 14 5 Bit 13 4 Bit 12 3 Bit 11 2 Bit 10 1 Bit 9 Bit 0 Bit 8
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Indeterminate after reset
Indeterminate after reset
Address: $0029 Bit 7 Read: Write: Reset: Bit 15
TCH1H 6 Bit 14 5 Bit 13 4 Bit 12 3 Bit 11 2 Bit 10 1 Bit 9 Bit 0 Bit 8
Indeterminate after reset
Address: $02A Bit 7 Read: Write: Reset: Bit 7
TCH1L 6 Bit 6 5 Bit 5 4 Bit 4 3 Bit 3 2 Bit 2 1 Bit 1 Bit 0 Bit 0
Indeterminate after reset
Figure 15-10. TIM Channel Registers (TCH0H/L:TCH1H/L)
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Timer Interface Module (TIM)
Data Sheet 153
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Timer Interface Module (TIM)
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Data Sheet 154 Timer Interface Module (TIM)
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Data Sheet -- MC68HC908QF4
Section 16. Development Support
16.1 Introduction
This section describes the break module, the monitor read-only memory (MON), and the monitor mode entry methods.
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16.2 Break Module (BRK)
The break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. Features include: * * * * Accessible input/output (I/O) registers during the break Interrupt Central processor unit (CPU) generated break interrupts Software-generated break interrupts Computer operating properly (COP) disabling during break interrupts
16.2.1 Functional Description When the internal address bus matches the value written in the break address registers, the break module issues a breakpoint signal (BKPT) to the system integration module (SIM). The SIM then causes the CPU to load the instruction register with a software interrupt instruction (SWI). The program counter vectors to $FFFC and $FFFD ($FEFC and $FEFD in monitor mode). The following events can cause a break interrupt to occur: * * A CPU generated address (the address in the program counter) matches the contents of the break address registers. Software writes a 1 to the BRKA bit in the break status and control register.
When a CPU generated address matches the contents of the break address registers, the break interrupt is generated. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the microcontroller unit (MCU) to normal operation. Figure 16-2 shows the structure of the break module. Figure 16-3 provides a summary of the I/O registers.
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Development Support
Data Sheet 155
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Development Support
PTA0/AD0/TCH0/KBI0 PTA1/AD1/TCH1/KBI1 DDRA PTA PTA2/IRQ/KBI2/TCLK PTA3/RST/KBI3 PTA4/OSC2/AD2/KBI4 PTA5/OSC1/AD3/KBI5 M68HC08 CPU PTB0 PTB1 PTB2 PTB3 PTB4 PTB5 PTB6 PTB7 CLOCK GENERATOR (OSCILLATOR)
SYSTEM INTEGRATION MODULE SINGLE INTERRUPT MODULE BREAK MODULE POWER-ON RESET MODULE KEYBOARD INTERRUPT MODULE 16-BIT TIMER MODULE COP MODULE VCC MODE PLLEN DATA BS OP1 GND REXT XTAL1 XTAL0 UPCLK PFD
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8-BIT ADC
DDRB
PTB
MC68HC908QF4 4096 BYTES USER FLASH
128 BYTES RAM
MONITOR ROM
UHF TRANSMITTER
VDD POWER SUPPLY VSS
RST, IRQ: Pins have internal (about 30K Ohms) pull up PTA[0:5]: High current sink and source capability PTA[0:5]: Pins have programmable keyboard interrupt and pull up
Figure 16-1. Block Diagram Highlighting BRK and MON Blocks
Data Sheet 156 Development Support
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Development Support Break Module (BRK)
ADDRESS BUS[15:8]
BREAK ADDRESS REGISTER HIGH 8-BIT COMPARATOR ADDRESS BUS[15:0] CONTROL 8-BIT COMPARATOR BREAK ADDRESS REGISTER LOW BKPT (TO SIM)
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ADDRESS BUS[7:0]
Figure 16-2. Break Module Block Diagram
Addr.
Register Name
Bit 7 R
6 R
5 R
4 R
3 R
2 R
1 SBSW Note(1) 0
Bit 0 R
Read: Break Status Register (BSR) $FE00 Write: See page 161. Reset: $FE02 Break Auxiliary Register Read: (BRKAR) Write: See page 160. Reset: Break Flag Control Read: Register (BFCR) Write: See page 161. Reset: Break Address High Read: Register (BRKH) Write: See page 160. Reset: Break Address Low Read: Register (BRKL) Write: See page 160. Reset: Break Status and Control Read: Register (BRKSCR) Write: See page 159. Reset:
Bit 7 0 BCFE 0 Bit15 0 Bit 7 0 BRKE 0
Bit 6 0 R
Bit 5 0 R
Bit 4 0 R
Bit 3 0 R
Bit 2 0 R
Bit 1 0 R
Bit 0 0 R
$FE03
$FE09
Bit14 0 Bit 6 0 BRKA 0
Bit13 0 Bit 5 0 0 0
Bit12 0 Bit 4 0 0 0 R
Bit11 0 Bit 3 0 0 0 = Reserved
Bit10 0 Bit 2 0 0 0
Bit9 0 Bit 1 0 0 0
Bit8 0 Bit 0 0 0 0
$FE0A
$FE0B
1. Writing a 0 clears SBSW.
= Unimplemented
Figure 16-3. Break I/O Register Summary
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Development Support
Data Sheet 157
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Development Support
When the internal address bus matches the value written in the break address registers or when software writes a 1 to the BRKA bit in the break status and control register, the CPU starts a break interrupt by: * * Loading the instruction register with the SWI instruction Loading the program counter with $FFFC and $FFFD ($FEFC and $FEFD in monitor mode)
The break interrupt timing is: * When a break address is placed at the address of the instruction opcode, the instruction is not executed until after completion of the break interrupt routine. When a break address is placed at an address of an instruction operand, the instruction is executed before the break interrupt. When software writes a 1 to the BRKA bit, the break interrupt occurs just before the next instruction is executed.
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* *
By updating a break address and clearing the BRKA bit in a break interrupt routine, a break interrupt can be generated continuously.
CAUTION:
A break address should be placed at the address of the instruction opcode. When software does not change the break address and clears the BRKA bit in the first break interrupt routine, the next break interrupt will not be generated after exiting the interrupt routine even when the internal address bus matches the value written in the break address registers.
16.2.1.1 Flag Protection During Break Interrupts The system integration module (SIM) controls whether or not module status bits can be cleared during the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status bits during the break state. See 16.2.2.5 Break Flag Control Register and the Break Interrupts subsection for each module. 16.2.1.2 TIM During Break Interrupts A break interrupt stops the timer counter. 16.2.1.3 COP During Break Interrupts The COP is disabled during a break interrupt with monitor mode when BDCOP bit is set in break auxiliary register (BRKAR).
Data Sheet 158 Development Support
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Development Support Break Module (BRK)
16.2.2 Break Module Registers These registers control and monitor operation of the break module: * * * * * Break status and control register (BRKSCR) Break address register high (BRKH) Break address register low (BRKL) Break status register (BSR) Break flag control register (BFCR)
16.2.2.1 Break Status and Control Register
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The break status and control register (BRKSCR) contains break module enable and status bits.
Address: $FE0B Bit 7 Read: Write: Reset: BRKE 0 6 BRKA 0 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 Bit 0 0 0
= Unimplemented
Figure 16-4. Break Status and Control Register (BRKSCR) BRKE -- Break Enable Bit This read/write bit enables breaks on break address register matches. Clear BRKE by writing a 0 to bit 7. Reset clears the BRKE bit. 1 = Breaks enabled on 16-bit address match 0 = Breaks disabled BRKA -- Break Active Bit This read/write status and control bit is set when a break address match occurs. Writing a 1 to BRKA generates a break interrupt. Clear BRKA by writing a 0 to it before exiting the break routine. Reset clears the BRKA bit. 1 = Break address match 0 = No break address match
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Development Support
Data Sheet 159
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16.2.2.2 Break Address Registers The break address registers (BRKH and BRKL) contain the high and low bytes of the desired breakpoint address. Reset clears the break address registers.
Address: $FE09 Bit 7 Read: Write: Reset: Bit 15 0 6 Bit 14 0 5 Bit 13 0 4 Bit 12 0 3 Bit 11 0 2 Bit 10 0 1 Bit 9 0 Bit 0 Bit 8 0
Figure 16-5. Break Address Register High (BRKH)
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Address: $FE0A Bit 7 Read: Write: Reset: Bit 7 0 6 Bit 6 0 5 Bit 5 0 4 Bit 4 0 3 Bit 3 0 2 Bit 2 0 1 Bit 1 0 Bit 0 Bit 0 0
Figure 16-6. Break Address Register Low (BRKL) 16.2.2.3 Break Auxiliary Register The break auxiliary register (BRKAR) contains a bit that enables software to disable the COP while the MCU is in a state of break interrupt with monitor mode.
Address: $FE02 Bit 7 Read: Write: Reset: 0 0 = Unimplemented 0 0 0 0 0 0 6 0 5 0 4 0 3 0 2 0 1 0 Bit 0 BDCOP 0
Figure 16-7. Break Auxiliary Register (BRKAR) BDCOP -- Break Disable COP Bit This read/write bit disables the COP during a break interrupt. Reset clears the BDCOP bit. 1 = COP disabled during break interrupt 0 = COP enabled during break interrupt.
Data Sheet 160 Development Support
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Development Support Break Module (BRK)
16.2.2.4 Break Status Register The break status register (BSR) contains a flag to indicate that a break caused an exit from wait mode. This register is only used in emulation mode.
Address: $FE00 Bit 7 Read: Write: Reset: R = Reserved 1. Writing a 0 clears SBSW. R 6 R 5 R 4 R 3 R 2 R 1 SBSW Note(1) 0 Bit 0 R
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Figure 16-8. Break Status Register (BSR) SBSW -- SIM Break Stop/Wait SBSW can be read within the break state SWI routine. The user can modify the return address on the stack by subtracting one from it. 1 = Wait mode was exited by break interrupt 0 = Wait mode was not exited by break interrupt 16.2.2.5 Break Flag Control Register The break control register (BFCR) contains a bit that enables software to clear status bits while the MCU is in a break state.
Address: $FE03 Bit 7 Read: BCFE Write: Reset: 0 R = Reserved R R R R R R R 6 5 4 3 2 1 Bit 0
Figure 16-9. Break Flag Control Register (BFCR)
BCFE -- Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Development Support
Data Sheet 161
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Development Support
16.2.3 Low-Power Modes The WAIT and STOP instructions put the MCU in low power- consumption standby modes. If enabled, the break module will remain enabled in wait and stop modes. However, since the internal address bus does not increment in these modes, a break interrupt will never be triggered.
16.3 Monitor Module (MON)
This subsection describes the monitor module (MON) and the monitor mode entry methods. The monitor allows debugging and programming of the microcontroller unit (MCU) through a single-wire interface with a host computer. Monitor mode entry can be achieved without use of the higher test voltage, VTST, as long as vector addresses $FFFE and $FFFF are blank, thus reducing the hardware requirements for in-circuit programming. Features include: * * * * * * * * * * Normal user-mode pin functionality on most pins One pin dedicated to serial communication between MCU and host computer Standard non-return-to-zero (NRZ) communication with host computer Execution of code in random-access memory (RAM) or FLASH FLASH memory security feature(1) FLASH memory programming interface Use of external 9.8304 MHz oscillator to generate internal frequency of 2.4576 MHz Simple internal oscillator mode of operation (no external clock or high voltage) Monitor mode entry without high voltage, VTST, if reset vector is blank ($FFFE and $FFFF contain $FF) Standard monitor mode entry if high voltage is applied to IRQ
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16.3.1 Functional Description Figure 16-10 shows a simplified diagram of monitor mode entry. The monitor module receives and executes commands from a host computer. Figure 16-11, Figure 16-12, and Figure 16-13 show example circuits used to enter monitor mode and communicate with a host computer via a standard RS-232 interface.
1. No security feature is absolutely secure. However, Motorola's strategy is to make reading or copying the FLASH difficult for unauthorized users. Data Sheet 162 Development Support MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Development Support Monitor Module (MON)
POR RESET
NO
IRQ = VTST?
YES
CONDITIONS FROM Table 16-1
PTA0 = 1, RESET VECTOR BLANK? YES
NO
PTA0 = 1, PTA1 = 1, AND PTA4 = 0? YES NORMAL USER MODE NORMAL MONITOR MODE
NO
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FORCED MONITOR MODE
INVALID USER MODE
HOST SENDS 8 SECURITY BYTES
IS RESET POR? NO
YES
YES
ARE ALL SECURITY BYTES CORRECT?
NO
ENABLE FLASH
DISABLE FLASH
MONITOR MODE ENTRY
DEBUGGING AND FLASH PROGRAMMING (IF FLASH IS ENABLED)
EXECUTE MONITOR CODE
YES
DOES RESET OCCUR?
NO
Figure 16-10. Simplified Monitor Mode Entry Flowchart
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Development Support
Data Sheet 163
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Development Support
Simple monitor commands can access any memory address. In monitor mode, the MCU can execute code downloaded into RAM by a host computer while most MCU pins retain normal operating mode functions. All communication between the host computer and the MCU is through the PTA0 pin. A level-shifting and multiplexing interface is required between PTA0 and the host computer. PTA0 is used in a wired-OR configuration and requires a pullup resistor. The monitor code has been updated from previous versions of the monitor code to allow enabling the internal oscillator to generate the internal clock. This addition, which is enabled when IRQ is held low out of reset, is intended to support serial communication/programming at 4800 baud in monitor mode by using the internal oscillator, and the internal oscillator user trim value OSCTRIM (FLASH location $FFC0, if programmed) to generate the desired internal frequency (1.0 MHz). Since this feature is enabled only when IRQ is held low out of reset, it cannot be used when the reset vector is programmed (i.e., the value is not $FFFF) because entry into monitor mode in this case requires VTST on IRQ. The IRQ pin must remain low during this monitor session in order to maintain communication. Table 16-1 shows the pin conditions for entering monitor mode. As specified in the table, monitor mode may be entered after a power-on reset (POR) and will allow communication at 9600 baud provided one of the following sets of conditions is met: * If $FFFE and $FFFF do not contain $FF (programmed state): - The external clock is 9.8304 MHz - IRQ = VTST If $FFFE and $FFFF contain $FF (erased state): - The external clock is 9.8304 MHz - IRQ = VDD (this can be implemented through the internal IRQ pullup) If $FFFE and $FFFF contain $FF (erased state): - IRQ = VSS (internal oscillator is selected, no external clock required)
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*
*
The rising edge of the internal RST signal latches the monitor mode. Once monitor mode is latched, the values on PTA1 and PTA4 pins can be changed. Once out of reset, the MCU waits for the host to send eight security bytes (see 16.3.2 Security). After the security bytes, the MCU sends a break signal (10 consecutive logic 0s) to the host, indicating that it is ready to receive a command.
Data Sheet 164 Development Support
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Development Support Monitor Module (MON)
VDD
VDD
10 k* RST (PTA3) MAX232 1 1 F + 3 4 C1+ 16 + C1- C2+ 15 + VTST 1 F 1 F 1 k VDD 9.8304 MHz CLOCK OSC1 (PTA5)
VDD 0.1 F
VDD
10 k* PTA1 IRQ (PTA2)
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1 F
+ 5 C2-
V+ 2 V- 6 1 F 10 9 74HC125 3 2 1 + 10 k 74HC125 5 6 4
VDD 9.1 V
10 k* PTA4 PTA0 VSS
DB9 2 3 5 7 8
* Value not critical
Figure 16-11. Monitor Mode Circuit (External Clock, with High Voltage)
VDD N.C. RST (PTA3) VDD 0.1 F MAX232 1 1 F + 3 4 1 F + 5 C2- DB9 2 3 5 7 8 10 9 2 74HC125 3 1 C1+ 16 + C1- C2+ 15 + 10 k* V+ 2 V- 6 1 F + 10 k 74HC125 5 6 4 VDD IRQ (PTA2) PTA4 N.C. 1 F 1 F PTA1 N.C. VDD 9.8304 MHz CLOCK OSC1 (PTA5)
PTA0 VSS
* Value not critical
Figure 16-12. Monitor Mode Circuit (External Clock, No High Voltage)
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Development Support Data Sheet 165
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VDD N.C. RST (PTA3)
VDD 0.1 F
MAX232 1 1 F + 3 4 C1+ 16
VDD +
N.C.
OSC1 (PTA5)
1 F 1 F + 10 k* IRQ (PTA2)
C1- C2+
15
PTA1
N.C.
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1 F
+ 5 C2-
V+ 2 V- 6 1 F 10 9 74HC125 3 2 1 + 10 k 74HC125 5 6 4
PTA4 VDD
N.C.
DB9 2 3 5 7 8
PTA0
VSS
* Value not critical
Figure 16-13. Monitor Mode Circuit (Internal Clock, No High Voltage)
16.3.1.1 Normal Monitor Mode RST and OSC1 functions will be active on the PTA3 and PTA5 pins respectively as long as VTST is applied to the IRQ pin. If the IRQ pin is lowered (no longer VTST) then the chip will still be operating in monitor mode, but the pin functions will be determined by the settings in the configuration registers (see Section 5. Configuration Register (CONFIG)) when VTST was lowered. With VTST lowered, the BIH and BIL instructions will read the IRQ pin state only if IRQEN is set in the CONFIG2 register. If monitor mode was entered with VTST on IRQ, then the COP is disabled as long as VTST is applied to IRQ.
Data Sheet 166 Development Support
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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MOTOROLA
Table 16-1. Monitor Mode Signal Requirements and Options
Communication Speed COP External Bus Clock Frequency Disabled Disabled Disabled Enabled X X X X 1.0 MHz (Trimmed) 9.8304 MHz 2.4576 MHz 9.8304 MHz 2.4576 MHz Baud Rate 9600 Provide external clock at OSC1. 9600 Provide external clock at OSC1. 4800 Internal clock is active. Comments
MC68HC908QF4 -- Rev. 1.0 X $FFFF (blank) 1 1 X X X X X X X $FFFF (blank) Not $FFFF -- COM [8] -- -- MOD0 MOD1 [12] [10] OSC1 [13] -- 1 1 0 X X X NC NC NC NC NC NC OSC1 VDD 11 13 15 9 7 8 10 12 14 16 5 6 3 4 RST IRQ PTA0 PTA4 PTA1 NC NC 1 2 GND
Mode
Serial Mode Communication Selection RST Reset IRQ (PTA2) (PTA3) Vector PTA0 PTA1 PTA4
Normal Monitor
VTST
VDD
Forced Monitor
VDD
VSS
User
X
Development Support
MON08 Function [Pin No.]
VTST [6]
RST [4]
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1. PTA0 must have a pullup resistor to VDD in monitor mode. 2. Communication speed in the table is an example to obtain a baud rate of 9600. Baud rate using external oscillator is bus frequency / 256 and baud rate using internal oscillator is bus frequency / 206. 3. External clock is a 9.8304 MHz oscillator on OSC1. 4. X = don't care 5. MON08 pin refers to P&E Microcomputer Systems' MON08-Cyclone 2 by 8-pin connector.
Development Support Monitor Module (MON)
Data Sheet
167
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16.3.1.2 Forced Monitor Mode If entering monitor mode without high voltage on IRQ, then startup port pin requirements and conditions, (PTA1/PTA4) are not in effect. This is to reduce circuit requirements when performing in-circuit programming. NOTE: If the reset vector is blank and monitor mode is entered, the chip will see an additional reset cycle after the initial power-on reset (POR). Once the reset vector has been programmed, the traditional method of applying a voltage, VTST, to IRQ must be used to enter monitor mode. If monitor mode was entered as a result of the reset vector being blank, the COP is always disabled regardless of the state of IRQ. If the voltage applied to the IRQ is less than VTST, the MCU will come out of reset in user mode. Internal circuitry monitors the reset vector fetches and will assert an internal reset if it detects that the reset vectors are erased ($FF). When the MCU comes out of reset, it is forced into monitor mode without requiring high voltage on the IRQ pin. Once out of reset, the monitor code is initially executing with the internal clock at its default frequency. If IRQ is held high, all pins will default to regular input port functions except for PTA0 and PTA5 which will operate as a serial communication port and OSC1 input respectively (refer to Figure 16-12). That will allow the clock to be driven from an external source through OSC1 pin. If IRQ is held low, all pins will default to regular input port function except for PTA0 which will operate as serial communication port. Refer to Figure 16-13. Regardless of the state of the IRQ pin, it will not function as a port input pin in monitor mode. Bit 2 of the Port A data register will always read 0. The BIH and BIL instructions will behave as if the IRQ pin is enabled, regardless of the settings in the configuration register. See Section 5. Configuration Register (CONFIG). The COP module is disabled in forced monitor mode. Any reset other than a power-on reset (POR) will automatically force the MCU to come back to the forced monitor mode. 16.3.1.3 Monitor Vectors In monitor mode, the MCU uses different vectors for reset, SWI (software interrupt), and break interrupt than those for user mode. The alternate vectors are in the $FE page instead of the $FF page and allow code execution from the internal monitor firmware instead of user code. NOTE: Exiting monitor mode after it has been initiated by having a blank reset vector requires a power-on reset (POR). Pulling RST (when RST pin available) low will not exit monitor mode in this situation.
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Data Sheet 168 Development Support
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Table 16-2 summarizes the differences between user mode and monitor mode regarding vectors. Table 16-2. Mode Difference
Functions Modes User Monitor Reset Vector High $FFFE $FEFE Reset Vector Low $FFFF $FEFF Break Vector High $FFFC $FEFC Break Vector Low $FFFD $FEFD SWI Vector High $FFFC $FEFC SWI Vector Low $FFFD $FEFD
16.3.1.4 Data Format
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Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format. Transmit and receive baud rates must be identical.
START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 STOP BIT NEXT START BIT
Figure 16-14. Monitor Data Format 16.3.1.5 Break Signal A start bit (logic 0) followed by nine logic 0 bits is a break signal. When the monitor receives a break signal, it drives the PTA0 pin high for the duration of two bits and then echoes back the break signal.
MISSING STOP BIT 2-STOP BIT DELAY BEFORE ZERO ECHO
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Figure 16-15. Break Transaction 16.3.1.6 Baud Rate The monitor communication baud rate is controlled by the frequency of the external or internal oscillator and the state of the appropriate pins as shown in Table 16-1. Table 16-1 also lists the bus frequencies to achieve standard baud rates. The effective baud rate is the bus frequency divided by 256 when using an external oscillator. When using the internal oscillator in forced monitor mode, the effective baud rate is the bus frequency divided by 206.
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Data Sheet 169
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16.3.1.7 Commands The monitor ROM firmware uses these commands: * * * * * * READ (read memory) WRITE (write memory) IREAD (indexed read) IWRITE (indexed write) READSP (read stack pointer) RUN (run user program)
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The monitor ROM firmware echoes each received byte back to the PTA0 pin for error checking. An 11-bit delay at the end of each command allows the host to send a break character to cancel the command. A delay of two bit times occurs before each echo and before READ, IREAD, or READSP data is returned. The data returned by a read command appears after the echo of the last byte of the command. NOTE: Wait one bit time after each echo before sending the next byte.
FROM HOST
READ
READ
ADDRESS HIGH
ADDRESS HIGH
ADDRESS LOW
ADDRESS LOW
DATA
4
1
4
1
4
1
3, 2
4 RETURN
ECHO Notes: 1 = Echo delay, approximately 2 bit times 2 = Data return delay, approximately 2 bit times
3 = Cancel command delay, 11 bit times 4 = Wait 1 bit time before sending next byte.
Figure 16-16. Read Transaction
FROM HOST
WRITE 3 ECHO 1
WRITE 3
ADDRESS HIGH
ADDRESS HIGH
ADDRESS LOW
ADDRESS LOW
DATA
DATA
1
3
1
3
1
2, 3
Notes: 1 = Echo delay, approximately 2 bit times 2 = Cancel command delay, 11 bit times 3 = Wait 1 bit time before sending next byte.
Figure 16-17. Write Transaction
A brief description of each monitor mode command is given in Table 16-3 through Table 16-8.
Data Sheet 170 Development Support MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Table 16-3. READ (Read Memory) Command
Description Operand Data Returned Opcode Read byte from memory 2-byte address in high-byte:low-byte order Returns contents of specified address $4A Command Sequence
SENT TO MONITOR
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READ
READ
ADDRESS ADDRESS ADDRESS HIGH HIGH LOW
ADDRESS LOW
DATA
ECHO
RETURN
Table 16-4. WRITE (Write Memory) Command
Description Operand Data Returned Opcode
FROM HOST
Write byte to memory 2-byte address in high-byte:low-byte order; low byte followed by data byte None $49 Command Sequence
WRITE
WRITE
ADDRESS HIGH
ADDRESS
HIGH
ADDRESS LOW
ADDRESS LOW
DATA
DATA
ECHO
Table 16-5. IREAD (Indexed Read) Command
Description Operand Data Returned Opcode Read next 2 bytes in memory from last address accessed 2-byte address in high byte:low byte order Returns contents of next two addresses $1A Command Sequence
FROM HOST
IREAD
IREAD
DATA
DATA
ECHO
RETURN
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Data Sheet 171
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Table 16-6. IWRITE (Indexed Write) Command
Description Operand Data Returned Opcode Write to last address accessed + 1 Single data byte None $19 Command Sequence
FROM HOST
IWRITE
IWRITE
DATA
DATA
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ECHO
A sequence of IREAD or IWRITE commands can access a block of memory sequentially over the full 64-Kbyte memory map. Table 16-7. READSP (Read Stack Pointer) Command
Description Operand Data Returned Opcode Reads stack pointer None Returns incremented stack pointer value (SP + 1) in high-byte:low-byte order $0C Command Sequence
FROM HOST
READSP
READSP
SP HIGH
SP LOW
ECHO
RETURN
Table 16-8. RUN (Run User Program) Command
Description Operand Data Returned Opcode Executes PULH and RTI instructions None None $28 Command Sequence
FROM HOST
RUN ECHO
RUN
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The MCU executes the SWI and PSHH instructions when it enters monitor mode. The RUN command tells the MCU to execute the PULH and RTI instructions. Before sending the RUN command, the host can modify the stacked CPU registers to prepare to run the host program. The READSP command returns the incremented stack pointer value, SP + 1. The high and low bytes of the program counter are at addresses SP + 5 and SP + 6.
SP HIGH BYTE OF INDEX REGISTER CONDITION CODE REGISTER SP + 1 SP + 2 SP + 3 SP + 4 SP + 5 SP + 6 SP + 7
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ACCUMULATOR LOW BYTE OF INDEX REGISTER HIGH BYTE OF PROGRAM COUNTER LOW BYTE OF PROGRAM COUNTER
Figure 16-18. Stack Pointer at Monitor Mode Entry 16.3.2 Security A security feature discourages unauthorized reading of FLASH locations while in monitor mode. The host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $FFF6-$FFFD. Locations $FFF6-$FFFD contain user-defined data. NOTE: Do not leave locations $FFF6-$FFFD blank. For security reasons, program locations $FFF6-$FFFD even if they are not used for vectors. During monitor mode entry, the MCU waits after the power-on reset for the host to send the eight security bytes on pin PTA0. If the received bytes match those at locations $FFF6-$FFFD, the host bypasses the security feature and can read all FLASH locations and execute code from FLASH. Security remains bypassed until a power-on reset occurs. If the reset was not a power-on reset, security remains bypassed and security code entry is not required. See Figure 16-19. Upon power-on reset, if the received bytes of the security code do not match the data at locations $FFF6-$FFFD, the host fails to bypass the security feature. The MCU remains in monitor mode, but reading a FLASH location returns an invalid value and trying to execute code from FLASH causes an illegal address reset. After receiving the eight security bytes from the host, the MCU transmits a break character, signifying that it is ready to receive a command. NOTE: The MCU does not transmit a break character until after the host sends the eight security bytes.
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Data Sheet 173
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VDD 4096 + 32 CGMXCLK CYCLES RST COMMAND 1 BYTE 2 ECHO BYTE 8 ECHO 2 BREAK 3 1 COMMAND ECHO
BYTE 1
BYTE 2
FROM HOST PA0 4 FROM MCU 1 BYTE 1 ECHO 3 1
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Notes: 1 = Echo delay, approximately 2 bit times 2 = Data return delay, approximately 2 bit times 3 = Wait 1 bit time before sending next byte 4 = Wait until clock is stable and monitor runs
Figure 16-19. Monitor Mode Entry Timing To determine whether the security code entered is correct, check to see if bit 6 of RAM address $80 is set. If it is, then the correct security code has been entered and FLASH can be accessed. If the security sequence fails, the device should be reset by a power-on reset and brought up in monitor mode to attempt another entry. After failing the security sequence, the FLASH module can also be mass erased by executing an erase routine that was downloaded into internal RAM. The mass erase operation clears the security code locations so that all eight security bytes become $FF (blank).
Data Sheet 174 Development Support
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Data Sheet -- MC68HC908QF4
Section 17. Electrical Specifications
17.1 Introduction
This section contains electrical and timing specifications.
17.2 Absolute Maximum Ratings
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Maximum ratings are the extreme limits to which the microcontroller unit (MCU) can be exposed without permanently damaging it. NOTE: This device is not guaranteed to operate properly at the maximum ratings. Refer to 17.5 DC Electrical Characteristics for guaranteed operating conditions.
Characteristic(1) Supply voltage Input voltage Mode entry voltage, IRQ pin Maximum current per pin excluding PTA0-PTA5, VDD, and VSS Maximum current for pins PTA0-PTA5 Storage temperature Maximum current out of VSS Maximum current into VDD 1. Voltages references to VSS. Symbol VDD VIN VTST I IPTA0--IPTA5 TSTG IMVSS IMVDD Value -0.3 to +6.0 VSS -0.3 to VDD +0.3 VSS -0.3 to +9.1 15 25 -55 to +150 100 100 Unit V V V mA mA C mA mA
NOTE:
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. For proper operation, it is recommended that VIN and VOUT be constrained to the range VSS (VIN or VOUT) VDD. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either VSS or VDD.)
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Electrical Specifications
Data Sheet 175
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Electrical Specifications
17.3 Functional Operating Range
Characteristic Operating temperature range (TL to TH) Operating voltage range(1) (VDDMIN to VDDMAX) -40 to 85C 0 to 70C 1. VDD must be above VTRIPR upon power on. Symbol TA Value -40 to 85 0 to 70 2.4 to 3.6 2.2 to 3.6 Unit C Temp Code C -- C --
VDD
V
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17.4 Thermal Characteristics
Characteristic Thermal resistance 32-pin TQFP I/O pin power dissipation Power dissipation(1) Constant(2) Average junction temperature Maximum junction temperature Symbol JA PI/O PD Value 72 User determined PD = (IDD x VDD) + PI/O = K/(TJ + 273C) PD x (TA + 273C) + PD2 x JA TA + (PD x JA) 150 Unit C/W W W
K TJ TJM
W/C C C
1. Power dissipation is a function of temperature. 2. K constant unique to the device. K can be determined for a known TA and measured PD. With this value of K, PD and TJ can be determined for any value of TA.
Data Sheet 176 Electrical Specifications
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Electrical Specifications DC Electrical Characteristics
17.5 DC Electrical Characteristics
Characteristic(1) Output high voltage (for VDD > 2.7 V) ILoad = -4 mA ILoad = -10 mA, PTA0, PTA1, PTA3-PTA5 only Output high voltage (for VDDMIN < VDD < VDDMAX) ILoad = -2 mA ILoad = -5 mA, PTA0, PTA1, PTA3-PTA5 only Symbol Min VDD -0.8 VDD -0.8 VDD -0.8 VDD -0.8 Typ(2) -- -- Max Unit
VOH
-- --
V
VOH
-- --
-- --
V
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Output low voltage (for VDD > 2.7 V) ILoad = 4 mA ILoad = 10 mA, PTA0, PTA1, PTA3-PTA5 only Output low voltage (for VDDMIN < VDD < VDDMAX) ILoad = 2 mA ILoad = 5 mA, PTA0, PTA1, PTA3-PTA5 only Maximum combined IOH (all I/O pins) Maximum combined IOL (all I/O pins) Input high voltage PTA0-PTA5, PTB0-PTB7 Input low voltage PTA0-PTA5, PTB0-PTB7 Input hysteresis DC injection current, all ports Total dc current injection (sum of all I/O) Digital I/O ports Hi-Z leakage current Typical at 25C Digital input only ports leakage current (PA2/IRQ/KBI2) Capacitance Ports (as input) Ports (as output) POR rearm voltage(3) POR rise time ramp rate(4) Monitor mode entry voltage Pullup resistors(5) PTA0-PTA5, PTB0-PTB7
VOL
-- --
-- --
0.8 0.8
V
VOL IOHT IOLT VIH VIL VHYS IINJ IINJTOT IIL IIN CIN COUT VPOR RPOR VTST RPU
-- -- -- -- 0.7 x VDD VSS 0.06 x VDD -2 -25 -1 -- -1 -- -- 0 0.035 VDD + 2.5 16
-- -- -- -- -- -- -- -- -- -- 0.1 -- -- -- -- -- -- 26
0.8 0.8 50 50 VDD 0.3 x VDD -- +2 +25 +1 -- +1 12 8 100 -- 9.1 36
V
mA mA V V V mA mA A A
pF mV V/ms V k
-- Continued on next page
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Electrical Specifications
Data Sheet 177
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Electrical Specifications
Characteristic(1) Low-voltage inhibit reset, trip falling voltage (LVR) Low-voltage inhibit reset, trip rising voltage (LVR) Low-voltage inhibit reset/recover hysteresis Low-voltage detect, trip falling voltage (LVD) Low-voltage detect, trip rising voltage (LVD) Low-voltage detect reset/recover hysteresis
Symbol VTRIPF VTRIPR VHYS VDTRIPF VDTRIPR VDHYS
Min 2.00 2.04 -- 2.20 2.21 --
Typ(2) 2.12 2.18 60 2.32 2.33 10
Max 2.24 2.30 -- 2.44 2.45 --
Unit V V mV V V mV
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1. VDD = VDDMIN to VDDMAX, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. Typical values reflect average measurements at VDD = 3.0 V, 25C only. 3. Maximum is highest voltage that POR is guaranteed. 4. If minimum VDD is not reached before the internal POR reset is released, the LVI will hold the part in reset until minimum VDD is reached. 5. RPU is measured at VDD = 3.0 V.
17.6 Control Timing
Characteristic(1) Internal operating frequency Internal clock period (1/fOP) RST input pulse width low IRQ interrupt pulse width low (edge-triggered) IRQ interrupt pulse period Symbol fOP (fBus) tcyc tRL tILIH tILIL Min -- 500 400 400 Note(2) Max 2 -- -- -- -- Unit MHz ns ns ns tcyc
1. VDD > 2.2 V, VSS = 0 Vdc; timing shown with respect to 20% VDD and 70% VDD unless otherwise noted. 2. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tcyc.
tRL RST tILIL tILIH IRQ
Figure 17-1. RST and IRQ Timing
Data Sheet 178 Electrical Specifications
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Electrical Specifications Typical 3.0-V Output Drive Characteristics
17.7 Typical 3.0-V Output Drive Characteristics
1.5
1.0 VDD-VOH (V) 3V PTA 3V PTB 0.5
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0.0 0 -5 -10 IOH (mA) -15 -20
Figure 17-2. Typical 3-Volt Output High Voltage versus Output High Current (25C)
1.5
1.0 VOL (V) 3V PTA 3V PTB 0.5
0.0 0 5 10 IOL (mA) 15 20
Figure 17-3. Typical 3-Volt Output Low Voltage versus Output Low Current (25C)
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Electrical Specifications
Data Sheet 179
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Electrical Specifications
17.8 Oscillator Characteristics
Characteristic Internal oscillator frequency(1) Crystal frequency, XTALCLK(1) External RC oscillator frequency, RCCLK(1) External clock reference frequency(1), (2) Crystal load capacitance(3) Symbol fINTCLK fOSCXCLK fRCCLK fOSCXCLK CL C1 C2 RB RS REXT Min -- 30 2 dc -- -- -- -- 270 Typ 4.0 32.768 -- -- 12.5 2 x CL 2 x CL 10 330 See Figure 17-4 Max -- 100 8 8 -- -- -- -- 360 Unit MHz kHz MHz MHz pF -- -- M k --
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Crystal fixed capacitance(3) Crystal tuning capacitance(3) Feedback bias resistor Series resistor RC oscillator external resistor 1. Bus frequency, fOP, is oscillator frequency divided by 4. 2. No more than 10% duty cycle deviation from 50%. 3. Consult crystal vendor data sheet.
12
10
8 fRCCLK (MHz) 3V 2.3V
MCU
OSC1
6
4
VDD
2
REXT
0 0 10 20 30 REXT (K) 40 50 60
Figure 17-4. Typical RC Oscillator Frequency versus REXT (25C)
Data Sheet 180 Electrical Specifications
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Electrical Specifications Supply Current Characteristics
17.9 Supply Current Characteristics
Characteristic Run mode VDD supply current(1) WAIT mode VDD supply current(2) Stop mode VDD supply current(3) 25C 0 to 70C -40 to 85C 25C with auto wake-up enabled Incremental current with LVI enabled at 25C 25C 0 to 70C -40 to 85C 25C with auto wake-up enabled Incremental current with LVI enabled at 25C 3.0 0.006 0.08 0.12 5.70 110 0.005 0.08 0.12 1.30 100 -- -- 2.0 -- -- -- -- 1.0 -- -- Voltage 3.0 2.2 3.0 2.2 Bus Freq. (MHz) 1 1 1 1 Symbol RIDD WIDD Typ 1.5 1.0 1.2 1.0 Max 2.5 1.5 2.0 1.0 Unit mA mA
A
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SIDD 2.2
A
1. Run (operating) IDD measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. All ports configured as inputs. Measured with all modules except ADC enabled. 2. Wait (operating) IDD measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. All ports configured as inputs. Measured with all modules except ADC enabled. 3. Stop IDD measured with all ports driven 0.2 V or less from rail. No dc loads. On the 8-pin versions, port B is configured as inputs with pullups enabled.
2.5
2
Run I DD (mA)
1.5
1
0.5
0 2 2.5 3 VDD (V)
INT OSC w/ ADC 32K CRYSTAL w/ ADC
INT OSC w/o ADC 32K CRYSTAL w/o ADC
3.5
4
Figure 17-5. Typical Run Current versus VDD (25C) (fBus = 1 MHz for Internal Oscillator, fBus = 8 kHz for Crystal Oscillator)
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1
0.8
Wait I DD (mA)
0.6
0.4
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0.2
0 2 2.5 3 VDD (V) INT OSC w/ ADC 32K CRYSTAL w/ ADC INT OSC w/o ADC 32K CRYSTAL w/o ADC 3.5 4
Figure 17-6. Typical Wait Current versus VDD (25C) fBus = 1 MHz for Internal Oscillator, fBus = 8 kHz for Crystal Oscillator)
10
8
Stop I DD (nA)
6
4
2
0 2 2.2 2.4 2.6 2.8 VDD (V) 3 3.2 3.4 3.6 3.8
Figure 17-7. Typical Stop Current versus VDD (25C)
Data Sheet 182 Electrical Specifications MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Electrical Specifications Analog-to-Digital (ADC) Converter Characteristics
17.10 Analog-to-Digital (ADC) Converter Characteristics
17.10.1 ADC Electrical Operating Conditions The ADC accuracy characteristics below are guaranteed over two operating conditions as stated here.
Characteristic ATD supply Condition A ADC internal clock Ambient temperature ATD supply Condition B ADC internal clock Ambient temperature Symbol VDD fADIC TA VDD fADIC TA Min 2.7 0.008 TL 2.3 8 0 Max 3.6 1 TH 2.7 63 TH Unit V MHz C V kHz C
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17.10.2 ADC Performance Characteristics
Characteristic Input voltages Resolution (1 LSB) Absolute accuracy (Total unadjusted error) Conversion range Power-up time Conversion time Sample time(1) Zero input reading(2) Full-scale reading(3) Input capacitance Input leakage(3) ADC supply current (VDD = 3 V) Condition A Condition B Condition A Condition B Symbol VADIN RES ETUE VAIN tADPU tADC tADS ZADI FADI CADI IIL IADAD Min VSS 10.5 8.99 -- -- VSS 16 16 5 00 FE -- -- Max VDD 14.1 10.5 1.5 2.0 VDD -- 17 -- 01 FF 8 1 Unit V mV LSB V tADIC cycles tADIC cycles tADIC cycles Hex Hex pF A mA Comments -- -- Includes quantization -- tADIC = 1/fADIC tADIC = 1/fADIC tADIC = 1/fADIC VIN = VSS VIN = VDD Not tested -- Enabled
Typical = 0.45
1. Source impedances greater than 10 k adversely affect internal RC charging time during input sampling. 2. Zero-input/full-scale reading requires sufficient decoupling measures for accurate conversions. 3. The external system error caused by input leakage current is approximately equal to the product of R source and input current.
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Data Sheet 183
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Electrical Specifications
17.11 Timer Interface Module Characteristics
Characteristic Timer input capture pulse width Timer input capture period Timer input clock pulse width Symbol tTH, tTL tTLTL tTCL, tTCH Min 2 Note(1) tcyc + 5 Max -- -- -- Unit tcyc tcyc ns
1. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tcyc.
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tTLTL tTH INPUT CAPTURE RISING EDGE
tTLTL tTL INPUT CAPTURE FALLING EDGE
tTLTL tTH INPUT CAPTURE BOTH EDGES tTL
tTCH TCLK tTCL
Figure 17-8. Timer Input Timing
Data Sheet 184 Electrical Specifications
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Electrical Specifications Memory Characteristics
17.12 Memory Characteristics
Characteristic RAM data retention voltage FLASH program bus clock frequency FLASH PGM/ERASE supply voltage (VDD) FLASH read bus clock frequency FLASH page erase time <1 k cycles >1 k cycles FLASH mass erase time FLASH PGM/ERASE to HVEN setup time FLASH high-voltage hold time FLASH high-voltage hold time (mass erase) FLASH program setup time FLASH program time FLASH return to read time FLASH cumulative program hv period FLASH endurance(4) FLASH data retention time(5) Symbol VRDR -- VPGM/ERASE fRead(1) tErase tMErase tNVS tNVH tNVHL tPGS tPROG tRCV(2) tHV(3) -- -- Min 1.3 1 2.7 0 0.9 3.6 4 10 5 100 5 30 1 -- 10 k 15 Typ -- -- -- -- 1 4 -- -- -- -- -- -- -- -- 100 k 100 Max -- -- 3.6 2 1.1 5.5 -- -- -- -- -- 40 -- 4 -- -- Unit V MHz V MHz ms ms s s s s s ms ms Cycles Years
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1. fRead is defined as the frequency range for which the FLASH memory can be read. 2. tRCV is defined as the time it needs before the FLASH can be read after turning off the high voltage charge pump, by clearing HVEN to 0. 3. tHV is defined as the cumulative high voltage programming time to the same row before next erase. tHV must satisfy this condition: tNVS + tNVH + tPGS + (tPROG x 32) tHV maximum. 4. Typical endurance was evaluated for this product family. For additional information on how Motorola defines Typical Endurance, please refer to Engineering Bulletin EB619. 5. Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25C using the Arrhenius equation. For additional information on how Motorola defines Typical Data Retention, please refer to Engineering Bulletin EB618.
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Electrical Specifications
Data Sheet 185
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Electrical Specifications
17.13 UHF Transmitter Module
This subsection provides electrical specifications and timing definitions for the UHF transmitter module. 17.13.1 UHF Module Electrical Characteristics Unless otherwise specified: * * * VCC = 3 V REXT = 12 k Operating temperature range (TA) = -40C to 85C RF output frequency: fCarrier = 433.92 MHz Reference frequency: fReference =13.56 MHz OOK modulation selected Output load is 50 resistor (see Figure 17-12)
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* * * *
Values refer to the circuit shown in the recommended application schematic (see Figure 12-5. Application Schematic in OOK Modulation, 315-MHz and 434-MHz Frequency Bands). Typical values reflect average measurement at VCC = 3 V, TA = 25C.
Parameter Test Conditions and Comments General Parameters TA 25C Supply current in standby mode TA = 60C TA = 85C 315 and 434 MHz bands, continuous wave, TA 85C 315 and 434 MHz bands, DATA = 0, -40C TA 85C 868 MHz band, DATA = 0, -40C TA 85C 868 MHz band, continuous wave, -40C TA 85C -- -- -- -- -- -- -- 0.1 7 40 11.6 4.4 4.6 11.8 5 30 100 13.5 6.0 6.2 15.1 nA nA nA mA mA mA mA Min Typ Max Unit
Supply current in transmission mode
-- Continued on next page
Data Sheet 186 Electrical Specifications
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Electrical Specifications UHF Transmitter Module
Parameter Supply voltage
Test Conditions and Comments
Min --
Typ 3 2.04 1.99 1.86 1.76 1.68 1.56
Max 3.6 2.11 2.06 1.95 1.84 1.78 1.67
Unit V V V V V V V
TA = -40C TA = -20C Shutdown voltage threshold TA = 25C TA = 60C TA = 85C TA = 125C
-- -- -- -- -- --
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RF Parameters (assuming a 50 matching network connected to the D.U.T. output) REXT value 315 and 434 MHz bands, with 50 matching network 868 MHz band, with 50 matching network Output power 315 and 434 MHz bands, -40C TA 125C 868 MHz band, -40C TA 125C Current and output power variation vs REXT value 314 and 434 MHz bands, with 50 matching network 315 and 434 MHz bands, with 50 matching network Harmonic 2 level 868 MHz band, with 50 matching network 315 and 434 MHz bands 868 MHz band 315 and 434MHz bands, with 50 matching network Harmonic 3 level 868 MHz band, with 50 matching network 315 and 434 MHz bands 868 MHz band Spurious level @ fCarrier f DATACLK Spurious level @ fCarrier f Reference 315 and 434 MHz bands 868 MHz band 315 MHz band 434 MHz band 868 MHz band -- -- -- 12 -- -- -3 -7 -- -- -- -- -- -- -- -- -- -- -- 5 1 0 -3 -0.35 -34 -49 -23 -38 -32 -57 -21 -48 -36 -29 -37 -44 -37 21 -- -- 3 0 -- -- -- -17 -27 -- -- -15 -39 -24 -17 -30 -34 -27 k dBm dBm dBm dBm dB/k mA/k dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc
-- Continued on next page
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Electrical Specifications
Data Sheet 187
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Electrical Specifications
Parameter Spurious level @ fCarrier/2
Test Conditions and Comments 315 MHz bands 434 MHz bands 868 MHz band
Min -- -- --
Typ -62 -80 -45
Max -53 -60 -39
Unit dBc dBc dBc -- dBc/Hz dBc/Hz s pF dBc kBit/s
RF spectrum
434 MHz bands 315 and 434 MHz bands, 175 kHz from f Carrier 868 MHz band, 175 kHz from f Carrier
See Figure 17-9, Figure 17-10, and Figure 17-11 -- -- -- -- -75 -73 400 1 20 20 90 -- -68 -66 1600 2 200 50 -- 10
Phase noise
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PLL lock-in time, tPLL_Lock_In XTAL1 input capacitance
fCarrier within 30 kHz from the final value, crystal series resistor = 150
OOK modulation Crystal resistance FSK modulation OOK modulation depth Data rate Microcontroller Interfaces Input low voltage Input high voltage Input hysteresis voltage Input current ENABLE pulldown resistor DATACLK output low voltage DATACLK output high voltage DATACLK rising time DATACLK falling time DATACLK settling time, tDATACLK_Settling Pins BAND, MODE, DATA @ high level Pins BAND, MODE, ENABLE, and DATA
-- -- 75 --
0 0.7 x VCC -- -- -- 0 CLoad = 2 pF 0.75 x VCC CLoad = 2 pF, measured from 20% to 80% of the voltage swing 45 < duty cycle fDATACLK < 55% -- -- --
-- -- -- -- 180 -- -- 250 150 800
0.3 x VCC VCC 150 100 -- 0.25 x VCC VCC 500 400 1800
V V mV nA k V V ns ns s
Data Sheet 188 Electrical Specifications
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Electrical Specifications UHF Transmitter Module
RESOLUTION BANDWIDTH: 100 KHZ
RESOLUTION BANDWIDTH: 30 KHZ
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Figure 17-9. RF Spectrum at 434-MHz Frequency Band Displayed with a 5-MHz Span
Figure 17-10. RF Spectrum at 434-MHz Frequency Band Displayed with a 50-MHz Span
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Electrical Specifications
Data Sheet 189
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Electrical Specifications
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Figure 17-11. RF Spectrum at 434-MHz Frequency Band Displayed with a 1.5-GHz Span 17.13.2 UHF Module Output Power Measurement The RF output levels given in the 17.13.1 UHF Module Electrical Characteristics are measured whith a 50- load directly connected to the pin RFOUT as shown in figure Figure 17-12. This wideband coupling method gives results independant of the application.
VCC IMPEDER: TDK MMZ1608Y102CTA00 RFOUT RF OUTPUT
100 pF 50
Figure 17-12. Output Power Measurement Configurations
Data Sheet 190 Electrical Specifications
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Electrical Specifications UHF Transmitter Module
The configuration shown in Figure 17-13(a) provides a better efficiency in terms of output power and harmonics rejection. Schematic in Figure 17-13(b) gives the equivalent circuit of the pin RFOUT and impeder as well as the matching network components for 434-MHz frequency band. NOTE: Note that the impeder is moved to the load side to decrease its influence (similar to dc bias through the antenna). Figure 17-14 gives the output power versus the REXT resistor value, in both cases with 50- load and with matching network.
VCC
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IMPEDER: TDK MMZ1608Y102CTA00
RFOUT
(a)
MATCHING NETWORK
RF OUTPUT
50 MATCHING NETWORK 330 pF L1
(b)
39 nH 3 k C0 R0
C3
50
RI IMPEDER
RL LOAD
1.5 pF 250 RFOUT PIN
Figure 17-13. Ouput Characteristic and Matching Network for 434-MHz Frequency Band
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Electrical Specifications
Data Sheet 191
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Electrical Specifications
OUTPUT POWER MEASUREMENT IN TYPICAL CONDITIONS (434 MHz - VCC = 3 V -25C) 8 REXT SPECIFIED RANGE
6 OUTPUT POWER WHEN MATCHED (dBm) -0.35 db/k # -0.35 mA/k
4
RFOUT LEVEL (dBm)
2 0
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-2
-4
OUTPUT POWER ON 50 LOAD (dBm)
-6 6 9 12 15 REXT (k) 18 21 24
Figure 17-14. Output Power at 434-MHz Frequency Band versus REXT Value
Data Sheet 192 Electrical Specifications
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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Data Sheet -- MC68HC908QF4
Section 18. Ordering Information and Mechanical Specifications
18.1 Introduction
This section provides ordering information and mechanical specifications for the 32-pin low-profile quad flat pack (LQFP).
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The package outline given here reflects the latest package drawing at the time of publication. To make sure that you have the latest package specification, contact your local Motorola Sales Office.
18.2 MC Order Numbers
Table 18-1. Available MC Order Numbers
MC Order Number MC908QF4CFJ MC908QF4FJ Temperature and package designators: C = -40C to +85C FJ = Low-profile quad flat pack (LQFP) Operating Temperature Range -40C to +85C 0C to +70C Package 32-pin LQFP 32-pin LQFP
MC908QF4CFJ
FAMILY PACKAGE DESIGNATOR TEMPERATURE RANGE BLANK = 0 TO 70C
Figure 18-1. Device Numbering System
MC68HC908QF4 -- Rev. 1.0 MOTOROLA Ordering Information and Mechanical Specifications
Data Sheet 193
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Ordering Information and Mechanical Specifications
18.3 32-Pin Plastic Low-Profile Quad Flat Pack (Case No. 873A)
A A1
32 25
4X
0.20 (0.008) AB T-U Z
1
-T- B B1 DETAIL Y
8 17
-U- V P V1 AE
9
AE
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DETAIL Y -Z-
4X
9
S1 S
0.20 (0.008) AC T-U Z
G -AB-
SEATING PLANE
DETAIL AD
-AC-
BASE METAL
N
F
8X
D
M_ R
0.20 (0.008)
M
AC T-U Z
0.10 (0.004) AC
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
J
CE
SECTION AE-AE
X DETAIL AD
Data Sheet 194 Ordering Information and Mechanical Specifications
GAUGE PLANE
0.250 (0.010)
H
W
K
Q_
DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X
MC68HC908QF4 -- Rev. 1.0 MOTOROLA
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-T-, -U-, -Z-
EE EE EE EE
Freescale Semiconductor, Inc.
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Home Page: www.freescale.com email: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 (800) 521-6274 480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku Tokyo 153-0064, Japan 0120 191014 +81 2666 8080 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate, Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 (800) 441-2447 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com
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Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part.
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